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SH-X: an embedded processor core for consumer appliances

Published: 29 September 2004 Publication History

Abstract

A SuperH™ embedded processor core SH-X implemented in a 130-nm CMOS process running at 400 MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches the 1.8 MIPS/MHz of the previous five-stage processor. The on-chip memory configuration is tuned for digital consumer appliances. A new resume-standby mode enables a standby current of less than 100, μA and a 3-ms recovery time. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems.

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Published In

cover image ACM Conferences
MEDEA '04: Proceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture
September 2004
62 pages
ISBN:9781450378192
DOI:10.1145/1152922
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 33, Issue 3
    Special issue: MEDEA 2004 workshop
    June 2005
    74 pages
    ISSN:0163-5964
    DOI:10.1145/1101868
    Issue’s Table of Contents
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Published: 29 September 2004

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