Proceedings of the 18th annual international symposium on Computer architecture

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ISCA '91: Proceedings of the 18th annual international symposium on Computer architecture

Go to Proceedings of the 18th annual international symposium on Computer architecture

April 1991

1991 Proceeding

Chairman:
Zvonko Vranesic

Publisher:

Association for Computing Machinery
New York
NY
United States

Conference:

ISCA91: 18th International Symposium on Computer Architecture Toronto Ontario Canada May 27 - 30, 1991

ISBN:

978-0-89791-394-2

Published:

01 April 1991

Sponsors:

SIGARCH, IEEE-CS

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ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

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1,818

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ISCA '91: Proceedings of the 18th annual international symposium on Computer architecture

1991

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The SNAP-1 parallel AI prototype

R. F. DeMara,
D. I. Moldovan

Pages 2–11https://doi.org/10.1145/115952.115954

- 9
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Total Downloads486
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GT-EP: a novel high-performance real-time architecture

Wei Siong Tan,
H. Russ,
Cecil O. Alford

Pages 13–21https://doi.org/10.1145/115952.115955

- 0
- 497
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Total Citations0
Total Downloads497
Last 12 Months131
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IXM2: a parallel associative processor

Tetsuya Higuchi,
Tatsumi Furuya,
Kenichi Handa,
Naoto Takahashi,
Hiroyasu Nishiyama,
Akio Kokubu

Pages 22–31https://doi.org/10.1145/115952.115956

- 5
- 494
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Total Downloads494
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Branch history table prediction of moving target branches due to subroutine returns

David R. Kaeli,
Philip G. Emma

Pages 34–42https://doi.org/10.1145/115952.115957

- 82
- 1,424
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Total Downloads1,424
Last 12 Months228
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An architecture for software-controlled data prefetching

Alexander C. Klaiber,
Henry M. Levy

Pages 43–53https://doi.org/10.1145/115952.115958

- 161
- 963
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Total Downloads963
Last 12 Months179
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Data prefetching in multiprocessor vector cache memories

John W. C. Fu,
Janak H. Patel

Pages 54–63https://doi.org/10.1145/115952.115959

- 122
- 891
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Total Downloads891
Last 12 Months124
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Reducing memory contention in shared memory multiprocessors

D. T. Harper

Pages 66–73https://doi.org/10.1145/115952.115960

- 1
- 481
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Total Citations1
Total Downloads481
Last 12 Months81
Last 6 weeks9

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Pseudo-randomly interleaved memory

B. Ramakrishna Rau

Pages 74–83https://doi.org/10.1145/115952.115961

- 87
- 2,296
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Total Citations87
Total Downloads2,296
Last 12 Months669
Last 6 weeks104

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Evaluation of memory system extensions

Kai Li,
Karin Petersen

Pages 84–93https://doi.org/10.1145/115952.115962

- 27
- 508
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Total Citations27
Total Downloads508
Last 12 Months76
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High performance interprocessor communication through optical wavelength division multiple access channels

Patrick W. Dowd

Pages 96–105https://doi.org/10.1145/115952.115963

- 22
- 599
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Total Citations22
Total Downloads599
Last 12 Months98
Last 6 weeks19

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Race-free interconnection networks and multiprocessor consistency

Anders Landin,
Erik Hagersten,
Seif Haridi

Pages 106–115https://doi.org/10.1145/115952.115964

- 39
- 630
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Total Citations39
Total Downloads630
Last 12 Months132
Last 6 weeks18

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Deadlock-free multicast wormhole routing in multicomputer networks

Xiaola Lin,
Lionel M. Ni

Pages 116–125https://doi.org/10.1145/115952.115965

- 79
- 1,583
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Total Citations79
Total Downloads1,583
Last 12 Months151
Last 6 weeks25

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Dynamic base register caching: a technique for reducing address bus width

Matthew Farrens,
Arvin Park

Pages 128–137https://doi.org/10.1145/115952.115966

- 64
- 566
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Total Citations64
Total Downloads566
Last 12 Months111
Last 6 weeks13

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Implementing a cache for a high-performance GaAs microprocessor

O. A. Olukotun,
T. N. Mudge,
R. B. Brown

Pages 138–147https://doi.org/10.1145/115952.115967

- 12
- 440
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Total Citations12
Total Downloads440
Last 12 Months96
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Classification and performance evaluation of instruction buffering techniques

Lizyamma Kurian,
Paul T. Hulina,
Lee D. Coraor,
Dhamir N. Mannai

Pages 150–159https://doi.org/10.1145/115952.115968

- 4
- 544
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Total Citations4
Total Downloads544
Last 12 Months159
Last 6 weeks17

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OHMEGA: a VLSI superscalar processor architecture for numerical applications

Masaitsu Nakajima,
Hiraku Nakano,
Yasuhiro Nakakura,
Tadahiro Yoshida,
Yoshiyuki Goi,
Yuji Nakai,
Reiji Segawa,
Takeshi Kishida,
Hiroshi Kadota

Pages 160–168https://doi.org/10.1145/115952.115969

- 5
- 420
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Total Citations5
Total Downloads420
Last 12 Months92
Last 6 weeks11

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An empirical study of the CRAY Y-MP processor using the Perfect club benchmarks

Sriram Vajapeyam,
Gurindar S. Sohi,
Wei-Chung Hsu

Pages 170–179https://doi.org/10.1145/115952.115970

- 7
- 533
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Total Citations7
Total Downloads533
Last 12 Months131
Last 6 weeks25

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Instruction level profiling and evaluation of the IBM/6000

Chriss Stephens,
Bryce Cogswell,
John Heinlein,
Gregory Palmer,
John P. Shen

Pages 180–189https://doi.org/10.1145/115952.115971

- 30
- 525
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Total Citations30
Total Downloads525
Last 12 Months132
Last 6 weeks27

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Performance prediction and tuning on a multiprocessor

R. T. Dimpsey,
R. K. Iyer

Pages 190–199https://doi.org/10.1145/115952.115972

- 9
- 437
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Total Citations9
Total Downloads437
Last 12 Months101
Last 6 weeks25

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Performance evaluation of a communication system for transputer-networks based on monitored event traces

C. W. Oehlrich,
A. Quick

Pages 202–211https://doi.org/10.1145/115952.115973

- 3
- 459
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Total Citations3
Total Downloads459
Last 12 Months131
Last 6 weeks21

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Chaos router: architecture and performance

S. Konstantinidou,
L. Snyder

Pages 212–221https://doi.org/10.1145/115952.115974

- 58
- 781
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Total Citations58
Total Downloads781
Last 12 Months160
Last 6 weeks23

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Scheduling pipelined communication in distributed memory multiprocessors for real-time applications

Shridhar B. Shukla,
Dharma P. Agrawal

Pages 222–231https://doi.org/10.1145/115952.115975

- 19
- 386
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Total Citations19
Total Downloads386
Last 12 Months86
Last 6 weeks17

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Detecting data races on weak memory systems

Sarita V. Adve,
Mark D. Hill,
Barton P. Miller,
Robert H. B. Netzer

Pages 234–243https://doi.org/10.1145/115952.115976

- 133
- 873
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Total Citations133
Total Downloads873
Last 12 Months138
Last 6 weeks26

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On the validity of trace-driven simulation for multiprocessors

Eric J. Koldinger,
Susan J. Eggers,
Henry M. Levy

Pages 244–253https://doi.org/10.1145/115952.115977

- 29
- 527
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Total Citations29
Total Downloads527
Last 12 Months101
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Comparative evaluation of latency reducing and tolerating techniques

Anoop Gupta,
John Hennessy,
Kourosh Gharachorloo,
Todd Mowry,
Wolf-Dietrich Weber

Pages 254–263https://doi.org/10.1145/115952.115978

- 156
- 1,338
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Total Citations156
Total Downloads1,338
Last 12 Months156
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IMPACT: an architectural framework for multiple-instruction-issue processors

Pohua P. Chang,
Scott A. Mahlke,
William Y. Chen,
Nancy J. Warter,
Wen-mei W. Hwu

Pages 266–275https://doi.org/10.1145/115952.115979

- 242
- 1,216
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Total Downloads1,216
Last 12 Months164
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Single instruction stream parallelism is greater than two

Michael Butler,
Tse-Yu Yeh,
Yale Patt,
Mitch Alsup,
Hunter Scales,
Michael Shebanow

Pages 276–286https://doi.org/10.1145/115952.115980

- 152
- 2,003
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Total Citations152
Total Downloads2,003
Last 12 Months334
Last 6 weeks41

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Exploiting fine-grained parallelism through a combination of hardware and software techniques

Stephen Melvin,
Yale Patt

Pages 287–296https://doi.org/10.1145/115952.115981

- 39
- 712
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Total Citations39
Total Downloads712
Last 12 Months123
Last 6 weeks15

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Comparison of hardware and software cache coherence schemes

Sarita V. Adve,
Vikram S. Adve,
Mark D. Hill,
Mary K. Vernon

Pages 298–308https://doi.org/10.1145/115952.115982

- 52
- 1,346
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Total Citations52
Total Downloads1,346
Last 12 Months276
Last 6 weeks37

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Modeling the performance of limited pointers directories for cache coherence

Richard Simoni,
Mark Horowitz

Pages 309–319https://doi.org/10.1145/115952.115983

- 10
- 529
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Total Citations10
Total Downloads529
Last 12 Months150
Last 6 weeks13

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Contributors

Zvonko G Vranesic
University of Toronto
- Publication Years1970 - 2013
- Publication counts57
- Citation count795
- Available for Download20
- Downloads (cumulative)7,687
- Downloads (12 months)1,083
- Downloads (6 weeks)144
- Average Downloads per Article384
- Average Citation per Article14
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Proceedings of the 18th annual international symposium on Computer architecture

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Recommendations

CompSysTech '17: Proceedings of the 18th International Conference on Computer Systems and Technologies
COMAD '12: Proceedings of the 18th International Conference on Management of Data
CSL-LICS '14: Proceedings of the Joint Meeting of the Twenty-Third EACSL Annual Conference on Computer Science Logic (CSL) and the Twenty-Ninth Annual ACM/IEEE Symposium on Logic in Computer Science (LICS)

Acceptance Rates

Overall Acceptance Rate 543 of 3,203 submissions, 17%

Year	Submitted	Accepted	Rate
ISCA '22	400	67	17%
ISCA '19	365	62	17%
ISCA '17	322	54	17%
ISCA '13	288	56	19%
ISCA '12	262	47	18%
ISCA '08	259	37	14%
ISCA '06	234	31	13%
ISCA '05	194	45	23%
ISCA '04	217	31	14%
ISCA '03	184	36	20%
ISCA '02	180	27	15%
ISCA '01	163	24	15%
ISCA '99	135	26	19%
Overall	3,203	543	17%

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Recommendations

CompSysTech '17: Proceedings of the 18th International Conference on Computer Systems and Technologies

COMAD '12: Proceedings of the 18th International Conference on Management of Data

CSL-LICS '14: Proceedings of the Joint Meeting of the Twenty-Third EACSL Annual Conference on Computer Science Logic (CSL) and the Twenty-Ninth Annual ACM/IEEE Symposium on Logic in Computer Science (LICS)

Acceptance Rates