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Robust level converter design for sub-threshold logic

Published: 04 October 2006 Publication History

Abstract

The large supply voltage difference between sub-threshlold core logic and I/O makes it extremely challenging to convert signals from core circuit to I/O circuit. In this paper, we propose two novel circuits, Clock Synchronizer and Reduced Swing Inverter to design dynamic and static level converters for sub-threshold logic. Circuit simulations shows that our level converters work at frequency > 500Khz between 20®C and 40®C with a supply voltage of 0.25V.

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Cited By

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  • (2023)A New 22 nm ULPLS Architecture to Detect 70 mV Minimum Input, Suitable for IOT Applications2023 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)10.1109/IEMENTech60402.2023.10423446(1-5)Online publication date: 18-Dec-2023
  • (2019)An Area Efficient Sub-threshold Voltage Level Shifter using a Modified Wilson Current Mirror for Low Power ApplicationsIETE Journal of Research10.1080/03772063.2019.161538968:1(559-565)Online publication date: 22-May-2019
  • (2018)A High Performance BPSK Trans Receiver Using Level Converter for Communication SystemsCommunication, Networks and Computing10.1007/978-981-13-2372-0_8(89-98)Online publication date: 10-Oct-2018
  • Show More Cited By

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    cover image ACM Conferences
    ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design
    October 2006
    446 pages
    ISBN:1595934626
    DOI:10.1145/1165573
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 04 October 2006

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    Author Tags

    1. level converter
    2. low power circuit design
    3. sub-threshold logic

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    ISLPED06
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    ISLPED06: International Symposium on Low Power Electronics and Design
    October 4 - 6, 2006
    Bavaria, Tegernsee, Germany

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    Overall Acceptance Rate 398 of 1,159 submissions, 34%

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    View all
    • (2023)A New 22 nm ULPLS Architecture to Detect 70 mV Minimum Input, Suitable for IOT Applications2023 7th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)10.1109/IEMENTech60402.2023.10423446(1-5)Online publication date: 18-Dec-2023
    • (2019)An Area Efficient Sub-threshold Voltage Level Shifter using a Modified Wilson Current Mirror for Low Power ApplicationsIETE Journal of Research10.1080/03772063.2019.161538968:1(559-565)Online publication date: 22-May-2019
    • (2018)A High Performance BPSK Trans Receiver Using Level Converter for Communication SystemsCommunication, Networks and Computing10.1007/978-981-13-2372-0_8(89-98)Online publication date: 10-Oct-2018
    • (2017)A low power high efficiency BPSK transceiver using level converter for communication applications2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI)10.1109/ICPCSI.2017.8392192(2625-2629)Online publication date: Sep-2017
    • (2011)A wide input voltage range level shifter circuit for extremely low-voltage digital LSIsIEICE Electronics Express10.1587/elex.8.8908:12(890-896)Online publication date: 2011
    • (2011)40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power ApplicationsACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197036916:3(1-17)Online publication date: 1-Jun-2011
    • (2009)Low energy level converter design for sub-Vth logicsProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509664(107-108)Online publication date: 19-Jan-2009
    • (2009)A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applicationsProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594288(225-230)Online publication date: 19-Aug-2009
    • (2008)Single stage static level shifter design for subthreshold to I/O voltage conversionProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393973(197-200)Online publication date: 11-Aug-2008

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