ABSTRACT
Although there has been extensive research on controlling leakage power, the fact that leaky transistors can act as a damping element for supply noise has been long ignored or unnoticed in the design community. This paper investigates the leakage induced damping effect that helps suppress the supply noise. By developing physics-based impedance models for active and leakage currents, we show that leakage, particularly gate tunneling leakage, provides more damping than strong-inversion current. Simulations were performed in a 32nm CMOS technology to validate our models under PVT variations and to explore the voltage dependent behavior of this phenomenon. Design example utilizing leakage induced damping such as decap assignment is discussed with results showing 15.6% saving in decap area.
- P. Gelsinger, Keynote talk at Intel Developer Forum, Feb. 2002Google Scholar
- B. Garben, etc. "Frequency Dependencies of Power Noise", IEEE Trans. On Adv. Packaging, vol. 25, no. 2, pp. 166--173, May 2002.Google ScholarCross Ref
- E. Hailu, D. Boerstler, K. Miki, etc. "A Circuit for Reducing Large Transient Current Effects on Processor Power Grids", Intl. Solid-State Circuits Conf., pp. 548--549, February 2006.Google Scholar
- N. Na, J. Choi, M. Swaminathan, J. P. Libous, etc. "Modeling and Simulation of Core Switching Noise for ASICs", IEEE Trans On Advanced Packaging, vol. 25, no. 1, pp. 4--11, February 2002.Google ScholarCross Ref
- M. Gowan, L. Biro and D. Jackson, "Power Considerations in the Design of the Alpha 21264 Microprocessor", Design Automation Conference, pp. 726--731, June 1998. Google ScholarDigital Library
- G. Ji, T. R. Arabi and G. Taylor, "Design and Validation of a Power Supply Noise Reduction Technique", IEEE Trans On Advanced Packaging, vol. 28, no. 3, pp. 445--448, August 2005.Google ScholarCross Ref
- P. Larsson, "Resonance and Damping in CMOS Circuits with On-Chip Decoupling Capacitance", IEEE Trans. On Circuits and Systems ? I: Fundamental Theory and Applications, vol. 45, no. 8, pp. 849--858, August 1998.Google ScholarCross Ref
- M. Ang, R. Salem and A. Taylor, "An On-Chip Voltage Regulator using Switched Decoupling Capacitors", Intl. Solid-State Circuits Conf., pp. 438--439, February 2000.Google ScholarCross Ref
- T. Rahal-Arabi, G. Taylor, J. Barkatullah, etc. "Enhancing Microprocessor Immunity to Power Supply Noise with Clock/Data Compensation", Symp. On VLSI Circuits, pp. 16--19, June 2005.Google Scholar
- International Technology Roadmap for Semiconductors, online: http://public.itrs.net/ .Google Scholar
- B. Garben, etc. "Influence of Damping and Voltage Dependent Leakage Resistance on Mid-Frequency Power Noise", IEEE Workshop on Sign. Propagation on Interconn., pp. 45--48, May 2004.Google ScholarCross Ref
- Predictive Technology Model, online: http://www.eas.asu.edu/~ptm/ .Google Scholar
- T. Sakurai, etc. "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas", IEEE J. of Solid-State Circuits, vol. 25, no. 2, pp. 584--594, April 1990.Google ScholarCross Ref
- S. Mukhopadhyay, C. Neau, etc. "Gate leakage Reduction for Scaled Devices Using Transistor Stacking", IEEE Trans. On VLSI Systems, vol. 11, no. 4, pp. 716--730, August 2003. Google ScholarDigital Library
Index Terms
- Modeling and analysis of leakage induced damping effect in low voltage LSIs
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