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View all- Martin G(2008)Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible ProcessorsJournal of Signal Processing Systems10.1007/s11265-007-0153-753:1-2(113-127)Online publication date: 1-Nov-2008
Although still negligible for state-of-the-art CMOS, gate leakage will become significant in the future for sub-100nm technologies, due to the scaling of oxide thickness. We propose several circuit techniques to control gate leakage based on the fact ...
The device scaling restricted due to the limitation of the subthreshold swing of the MOS transistor, which is not less than 60 mV/dec. The researchers are concentrating more on power efficient techniques for advanced, more featured, ...
low power design is most required nowadays due to scaling down the technology where minimizing the voltage level is the most effective way to minimize the power consumption. This paper presents the design and implementation of a low power Complementary ...
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