article

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters

Authors:

Kaushik RoyAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11, Issue 4

Pages 848 - 879

https://doi.org/10.1145/1179461.1179464

Published: 01 October 2006 Publication History

Abstract

Variability in process parameters is making accurate timing analysis of nano-scale integrated circuits an extremely challenging task. In this article, we propose a new algorithm for statistical static timing analysis (SSTA) using levelized covariance propagation (LCP). The algorithm simultaneously considers the effect of die-to-die variations in process parameters as well as within-die variation, including systematic and random variations. In order to efficiently handle complicated process variation models while contending with the arbitrary correlation among timing signals, we employ a compact form of the levelized statistical data structure. Furthermore, we propose two enhancements to the LCP algorithms to the make it practical for the analysis of large sized circuits. Results on several ISCAS'85 benchmark circuits in predictive 70nm technology show an average of 0.19% and 0.57% errors in the mean and standard deviation, respectively, of timing analysis using the proposed technique, as compared to the Monte Carlo-based approach.

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Cited By

Champac VGarcia Gervacio JChampac VGarcia Gervacio J(2018)Process VariationsTiming Performance of Nanometer Digital Circuits Under Process Variations10.1007/978-3-319-75465-9_3(41-69)Online publication date: 19-Apr-2018
https://doi.org/10.1007/978-3-319-75465-9_3
Moreno JRenovell MChampac V(2016)Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239793424:1(378-382)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2397934
Copetti TMedeiros GPoehls LVargas FKostin SJenihhin MRaik JUbar R(2016)Gate-level modelling of NBTI-induced delays under process variations2016 17th Latin-American Test Symposium (LATS)10.1109/LATW.2016.7483343(75-80)Online publication date: Apr-2016
https://doi.org/10.1109/LATW.2016.7483343
Show More Cited By

Index Terms

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
2. Software and its engineering
  1. Software creation and management
    1. Designing software
      1. Software implementation planning
        Software design techniques
    2. Software development process management

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 11, Issue 4

October 2006

177 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1179461

Issue’s Table of Contents

Copyright © 2006 ACM.

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 October 2006

Published in TODAES Volume 11, Issue 4

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Cited By

Champac VGarcia Gervacio JChampac VGarcia Gervacio J(2018)Process VariationsTiming Performance of Nanometer Digital Circuits Under Process Variations10.1007/978-3-319-75465-9_3(41-69)Online publication date: 19-Apr-2018
https://doi.org/10.1007/978-3-319-75465-9_3
Moreno JRenovell MChampac V(2016)Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239793424:1(378-382)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2397934
Copetti TMedeiros GPoehls LVargas FKostin SJenihhin MRaik JUbar R(2016)Gate-level modelling of NBTI-induced delays under process variations2016 17th Latin-American Test Symposium (LATS)10.1109/LATW.2016.7483343(75-80)Online publication date: Apr-2016
https://doi.org/10.1109/LATW.2016.7483343
Martin PWanner LSrivastava M(2015)Runtime Optimization of System Utility with Variable HardwareACM Transactions on Embedded Computing Systems10.1145/265633814:2(1-25)Online publication date: 17-Feb-2015
https://dl.acm.org/doi/10.1145/2656338
García-Gervacio JNocua AChampac V(2015)Screening small-delay defects using inter-path correlation to reduce reliability riskMicroelectronics Reliability10.1016/j.microrel.2015.03.00755:6(1005-1011)Online publication date: May-2015
https://doi.org/10.1016/j.microrel.2015.03.007
Garcia-Gervacio JMartinez-Castillo JChampac V(2014)Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies2014 15th Latin American Test Workshop - LATW10.1109/LATW.2014.6841909(1-6)Online publication date: Mar-2014
https://doi.org/10.1109/LATW.2014.6841909
Wanner LApte CBalani RGupta PSrivastava M(2013)Hardware Variability-Aware Duty Cycling for Embedded SensorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.220332521:6(1000-1012)Online publication date: 1-Jun-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2203325
Kounalakis ESotiriou CZebilis V(2011)Statistical Timing-Based Post-Placement Leakage RecoveryProceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2011.47(102-107)Online publication date: 4-Jul-2011
https://dl.acm.org/doi/10.1109/ISVLSI.2011.47
Kounalakis ESotiriou C(2011)SCPlace: A statistical slack-assignment based constructive placer2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770717(1-8)Online publication date: Mar-2011
https://doi.org/10.1109/ISQED.2011.5770717
Siddiqua TGurumurthi SStan M(2011)Modeling and analyzing NBTI in the presence of Process Variation2011 12th International Symposium on Quality Electronic Design10.1109/ISQED.2011.5770699(1-8)Online publication date: Mar-2011
https://doi.org/10.1109/ISQED.2011.5770699
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