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Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated

Published: 12 November 2006 Publication History

Abstract

Building state-of-the-art processors is expensive and time consuming. Once the design is finalized and implemented, simulations are used to evaluate functionality and performance of the system. The Sim-alpha processor simulator is one of the most important tools for performance evaluations. Enhancing processor simulators is one of the major research field and many studies are underway related to this area. Current, open source, processor simulators do not account for the influences caused by multi-processing. In this study, we had shown that most processor simulations only test one program at a time on a virtual processor. The goal of the project was to demonstrate how processor simulators work when external influences are incorporated. Hardware or software interrupts are events that alter sequence of instructions executed by a processor. A context switch occurs when a multitasking operating system suspends the currently running process, and starts executing another. An additional code was added to the Sim-alpha program to allow for context switch. Benchmarks were executed with and without time slice context switch as well as different time slices. The results had shown that when the number of cycles before flushing the cache increases, the miss rate will decrease. For example if we are flushing the cache every 150 cycles, the cache miss rate is 48% compare to 2% without flushing the cache. The effect of flushing the cache is significant on the cache performance of processor simulators. In real life environments, processor must support multiple processes. We demonstrated with a simple change in the code that these simulators can have a more realistic workload. The effect of flushing the cache is significant on the cache performance of processor simulators. Current models do not account for this and may over estimate the performance gains of a particular processor design.

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Cited By

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  • (2017)SimBench: A portable benchmarking methodology for full-system simulators2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS.2017.7975293(217-226)Online publication date: Apr-2017
  • (2010)On the Thermal Attack in Instruction CachesIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2009.167:2(217-223)Online publication date: 1-Apr-2010
  • (2008)Low-Cost Application-Aware DVFS for Multi-core ArchitectureProceedings of the 2008 Third International Conference on Convergence and Hybrid Information Technology - Volume 0210.1109/ICCIT.2008.124(106-111)Online publication date: 11-Nov-2008

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cover image ACM Conferences
SIGAda '06: Proceedings of the 2006 annual ACM SIGAda international conference on Ada
November 2006
92 pages
ISBN:1595935630
DOI:10.1145/1185642
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 12 November 2006

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Author Tags

  1. cache
  2. context switches
  3. cpu
  4. processor simulators
  5. sim-alpha

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SIGAda '06
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SIGAda '06: ACM SIGAda Annual International Conference
November 12 - 16, 2006
New Mexico, Albuquerque, USA

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Cited By

View all
  • (2017)SimBench: A portable benchmarking methodology for full-system simulators2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS.2017.7975293(217-226)Online publication date: Apr-2017
  • (2010)On the Thermal Attack in Instruction CachesIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2009.167:2(217-223)Online publication date: 1-Apr-2010
  • (2008)Low-Cost Application-Aware DVFS for Multi-core ArchitectureProceedings of the 2008 Third International Conference on Convergence and Hybrid Information Technology - Volume 0210.1109/ICCIT.2008.124(106-111)Online publication date: 11-Nov-2008

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