Subhashis Majumder
Abstract
This article addresses the problem of recursively bipartitioning a given floorplan F using monotone staircases. At each level of the hierarchy, a monotone staircase from one corner of F to its opposite corner is identified, such that (i) the two parts of the bipartition are nearly equal in area (or in the number of blocks), and (ii) the number of nets crossing the staircase is minimal. The problem of area-balanced bipartitioning is shown to be NP-hard, and a maxflow-based heuristic is proposed. Such a hierarchy may be useful to repeater placement in deep-submicron physical design, and also to global routing.
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Index Terms
- Hierarchical partitioning of VLSI floorplans by staircases
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Reviews
I-Lun Tseng
The partitioning of floorplans is an important topic in the field of very large-scale integration (VLSI) physical design automation. Proper partitioning of floorplans can lead to not only efficient insertion of repeaters, but also efficient global and channel routing. As a result, the quality of physical layouts can be improved and the design time can be reduced. In this paper, a floorplan is defined to contain a number of rectangular blocks, and each of those blocks may have associated nets. An ms-cut is a monotone staircase that partitions rectangular blocks of a floorplan into two groups, and the monotone staircase cuts those blocks from the floorplan's bottom-left corner to the floorplan's top-right corner; the staircase does not go down or go left when it cuts the floorplan. Since a floorplan can have many different ms-cuts, there are a variety of problems with regard to the partitioning of a floorplan with ms-cuts. A number of floorplan partitioning problems are discussed in the paper. The min-cut problem P c is to find an ms-cut that minimizes the number of nets crossing the two partitions. The number-balance problem P n is to find an ms-cut that balances the numbers of rectangular blocks for the two partitions, whereas the area-balance problem P A is to find an ms-cut that balances the areas of the two partitions. Furthermore, there is the number-balanced min-cut problem P nc and the area-balanced min-cut problem P Ac ; the two problems consider the number of crossing nets as well as one of the balancing factors. Before this paper was published, it had already been proven that problems P c and P n are polynomial time solvable. The paper goes one step further and attacks other floorplan partitioning problems: it proves that P A and P Ac are nondeterministic polynomial time (NP) hard, and conjectures that P nc is also NP hard. Furthermore, the paper proposes a heuristic for solving these difficult problems. The heuristic is based on a max-flow min-cut method, and is capable of partitioning (or bi-partitioning) a floorplan hierarchically. The paper discusses a number of floorplan partitioning problems. These problems are clearly presented and are interesting. The heuristic proposed for solving some of these problems is flexible and efficient. Moreover, partitioning a floorplan using monotone staircase cuts can be beneficial to other VLSI physical design processes. Online Computing Reviews Service
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