Soheil Aminzadeh
ABSTRACT
The main approach of this paper is utilizing bio-inspired evolutionary strategies for high level test synthesis. In this paper a genetic algorithm (GA) is implemented to schedule a data-flow graph considering latency. Also, module binding is performed with another GA concurrently, considering resource constraints. The register allocation is performed using another GA which minimizes the number of registers. Then a co-evolutionary strategy merges the results of these three solutions, targeting testability improvement. Experimental results show using the proposed approach results in improvement in fault coverage with no or negligible overhead in area and delay.
- M. C. McFarland, A. C. Parker, and R. Camposano, "Tutorial on High-Level Synthesis," Proceedings of 25th Design Automation Conference, pp. 330--336, California, June 1988. Google Scholar
Digital Library
- M. C. McFarland, A. C. Parker, and R. Camposano, "The High-Level Synthesis of Digital Systems," Proceedings of the IEEE, Vol. 78, No. 2, pp. 310--318, Feb 1990.Google ScholarCross Ref
- Michael L. Bushnell, Vishwani D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000.Google Scholar
- S. Dey, A. Raghunatan, and R. K. Roy, "Considering Testability during High-Level Design," ASP DAC, pp. 205--210, 1998.Google Scholar
- L.J. Avra, E.J. McCluskey, "High-level synthesis of testable design: An overview of university systems," IEEE International Test Conference - Test Synthesis Seminar, Washington D.C., 1994.Google Scholar
- K.D. Wagner, S. Dey, "High-Level Synthesis for Testability: a Survey and Perspective", Proceedings of Design Automation Conference, pp.131--136, 1996. Google ScholarDigital Library
- Mike Tien, Chien Lee, High Level Test Synthesis of Digital VLSI Circuits, Artech House Press, 1997. Google ScholarDigital Library
- T. Lee, N.K. Jha, and W.H. Wolf, "Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments," Proceedings of Design Automation Conference, pp. 292--297, 1993. Google ScholarDigital Library
- J. Steensma, F. Catthor, and H.D. Man, " Test of high Throughput Data Paths with Symbolic Controllability and Observability Descriptions," In Proceedings of 6th Workshop New Directions for testing, pp 67--76, May 1992.Google Scholar
- Frank F. Hsu, Janak H. Patel, "High-Level Variable Selection for Partial-Scan Implementation," In Proc. of the IEEE International Conference on Computer Aided Design, pp. 79--84, 1998. Google ScholarDigital Library
- M.L. Flottes, R. Pires, and B. Rouzeyre, L. Volpe, "Scanning Data Paths: A Fast and Effective Partial Scan Technique," Proceedings of DATE, pp. 158--165, Paris, February 1998. Google ScholarDigital Library
- Saeed Safari, Amir Hossein Jahangir, Hadi Esmaeilzadeh, "A parameterized graph-based framework for high-level test synthesis", INTEGRATION, the VLSI journal 39, pp. 363--381, 2006. Google ScholarDigital Library
- T. Yang, Z. Peng, "An Efficient Algorithm to Integrated Scheduling and Allocation in High-Level Test Synthesis," Proceedings of DATE, pp. 74--81, Paris, February 1998. Google ScholarDigital Library
- R. Camposano, W. Rosenstiel, "Synthesizing Circuits from Behavioral Descriptions," IEEE Transactions on CAD/ICAS, Vol. 8, No. 2, pp. 171--180, February 1989.Google ScholarDigital Library
- F. J. Kurdahi, A.C. Parker, "REAL: A Program for Register Allocation," Proceedings of Design Automation Conference, pp. 210--215, June 1987. Google ScholarDigital Library
- A.E. Eiben and J.E. Smith, Introduction to Evolutionary Computing. Heidelberg: Springer, 2003. Google ScholarDigital Library
- D. Beasley, D. R. Bull, and R. R. Martin, "An overview of genetic algorithms: Part 1, fundamentals," University Computing, vol. 15, no. 2, pp. 58--69, 1993.Google Scholar
- P.G. Paulin, J.P. Knight, E.F. Girczyc, "HAL: a multi-paradigm approach to automatic data path synthesis," Proceedings of the Design Automation Conference, pp. 263--270, June 1989. Google ScholarDigital Library
- M.K. Dhodhi and et. al., "Datapath synthesis using a problem-space genetic algorithm," Proc. Of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, pp 934--944, Aug. 1995. Google ScholarDigital Library
- HOPE (version 2.0), Dong S. Ha ([email protected]), Web: http://www.ee.vt.edu/ha, Virginia Polytechnic Institute & State University.Google Scholar
Index Terms
- Co-evolutionary high-level test synthesis
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