V. Gherman
ABSTRACT
A special logic synthesis problem is considered for Booleanfunctions which have large don't care sets and are irregular. Here, a function is considered as irregular if the input assignmentsmapped to specified values ('1' or '0') are randomly spread overthe definition space. Such functions can be encountered in the field of design for test. The proposed method uses ordered BDDs forlogic manipulations and generates free BDD-like covers. For the considered benchmark functions, implementations were found witha significant reduction of the node/gate count as compared to SISor to methods offered by a state-of-the-art BDD package.
- S.B. Akers "Binary Decision Diagrams," Trans. on Computers, Vol. C-27, No. 6, 1978, 509--516.Google Scholar
- B. Becker "Synthesis For Testability: Binary Decision Diagrams," STACS. LNCS, Vol. 577, Springer Verlag, 1992, 501--512. Google ScholarDigital Library
- R.K. Brayton et al. "MIS: A Multiple-Level Logic Optimization System," Trans. on CAD, 1987, 1062--1081.Google Scholar
- R.K. Brayton et al. "Logic Minimization Algorithms for VLSI Synthesis," Kluver Academic Publishers, 1997. Google ScholarDigital Library
- R.E. Bryant "Graph-Based Algorithms for Boolean Function Manipulation," Trans. on Computers, Vol. C-35, No. 8, 1986, 677--691. Google ScholarDigital Library
- R.E. Bryant "On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication," Trans. on Computers, Vol. 40, No. 2, 1991, 205--213. Google ScholarDigital Library
- S.-C. Chang et al. "Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions," European Design and Test Conference, 1994, 620--624.Google Scholar
- O. Coudert et al. "Verification of Sequential Machines using Boolean Functional Vectors," IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, 1989, 111--128.Google Scholar
- O. Coudert, J. Madre "Verification of Synchronous Sequential Machines Based on Symbolic Execution," Automatic Verification Methods for Finite State Systems, Springer-Verlag, 1990, 365--373. Google ScholarDigital Library
- V. Gherman et al. "Efficient Pattern Mapping for Deterministic Logic BIST," Int. Test Conference, 2004, pp. 48--56. Google ScholarDigital Library
- W. Günther, R. Drechsler "Minimization of Free BDDs," INTEGRATION, The VLSI Journal, 32 (1--2), Nov. 2002, 41--59. Google ScholarDigital Library
- J. Hlavicka, P. Fiser "BOOM - a Heuristic Boolean Minimizer," Int. Conference on Computer Aided Design, 2001, pp. 439--442. Google ScholarDigital Library
- Y. Hong et al. "Sibling-Substitution-Based BDD Minimization using Don't Cares," Trans. on CAD of Integrated Circuits and Systems, 2000, pp. 44--55. Google ScholarDigital Library
- B. Koenemann et al. "A SmartBIST Variant with Guaranteed Encoding," Asian Test Symposium, 2001, 325--300. Google ScholarDigital Library
- R. Michalski "On the Quasi-Minimal Solution of the General Covering Problem," Int. Symposium on Information Processing (FCIP 69) (Switching Circuits), Vol. A3, 1969, 125--128.Google Scholar
- S. Minato "Binary Decision Diagrams and Applications For VLSI Computer-Aided Design," Kluver Academic Publishers, 1997. Google ScholarDigital Library
- A.L. Oliveira et al. "Exact Minimization of Binary Decision Diagrams using Implicit Techniques," Trans. on Computers, Vol. 47, No. 11, 1998, 1282--1296. Google ScholarDigital Library
- S. Panda et al. "Symmetry Detection and Dynamic Variable Ordering of Decision Diagrams," Int. Conference on Computer-Aided Design, San Jose, CA, 1994, 628--631. Google ScholarDigital Library
- J. Rajski et al. "Embedded deterministic test for low cost manufacturing test," Int. Test Conf., 2002, 301--310. Google ScholarDigital Library
- M. Sauerhoff et al. "On the Complexity of Minimizing the OBDD Size for Incompletely Specified Functions," Trans. on CAD of Integrated Circuits and Systems, Vol. 15, 1996, 1435--1437. Google ScholarDigital Library
- C. Scholl et al. "BDD Minimization using Symmetries," Trans. on CAD of Integrated Circuits and Systems, Vol. 18, No 2, 1999, 81--100. Google ScholarDigital Library
- E. Sentovich et al. "Sequential Circuit Design Using Synthesis and Optimization," ICCD, 1992, 328--333. Google ScholarDigital Library
- T. Shiple et al. "Heuristic Minimization of BDDs Using Don't Cares," Design Automation Conference, 1994, 225--231. Google ScholarDigital Library
- D. Sieling, I. Wegener "Graph Driven BDDs - a New Data Structure for Boolean Functions," Theoretical Computer Science, Vol. 141, No.1--2, 1995, 283--310. Google ScholarDigital Library
- Y. Tang et al. "X-Masking during Logic BIST and its Impact on Defect Coverage," Int. Test Conference, 2004, 442--451. Google ScholarDigital Library
- N.A. Touba, E.J. McCluskey "Altering a Pseudo-random Bit Sequence for Scan-Based BIST," Int. Test Conf., 1996, 167--175. Google ScholarDigital Library
- http://vlsi.colorado.edu/~fabio/CUDD/cuddIntro.htmlGoogle Scholar
- http://www.ra.informatik.unistuttgart.de/~ghermanv/benchmarks/index.phtmlGoogle Scholar
Index Terms
- Synthesis of irregular combinational functions with large don't care sets
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