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An evolutionary approach for standard-cell library reduction

Published: 11 March 2007 Publication History

Abstract

Typically, commercially available standard-cell libraries consist of a large set of items, including cells optimized with respect to speed, area or power consumption. A large number of cells makes the synthesis process and the library maintenance quite demanding. By using a reduced set of properly-selected cells, such efforts can be reduced, without critically affecting performance. This paper introduces an innovative library-reduction strategy, based on a evolutionary algorithm, which allows for selecting an arbitrarily small subset of cells. Library compaction is strictly related to the features of the actual synthesis tool, and is tuned by means of a large set of benchmark circuits, so that it produces results suitable for general-purpose circuit design. Different technologies were accounted for, analyzing dependence of the area, time and power figures on the library cell count. Performance, with respect to full-size library synthesis, do not appreciably degrades, and in several cases actually improves. Synthesis time decreases and library maintenance and characterization tasks can thus be significantly reduced.

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C. Piguet, et al., "Low-Power Low-Voltage Library Cells and Memories," in Proceedings of the 8th International Conference on Electronics, Circuits and Systems, pp. 1521--1524, September 2001.
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N. M. Duc and T. Sakurai, "Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies," in Proceedings of the Asia and South Pacific Design Automation Conference, pp. 475--480, January 2000.
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Synopsys Inc., Design Compiler User Guide. http://www.synopsys.com, August 2001.
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ITC'99 Web page. http://www.cad.polito.it/tools/itc99.html.
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L. Wall, T. Christiansen and J. Orwant, Programming Perl, Third Edition. O'Reilly, July 2002.
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  • (2023)Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flowIET Computers & Digital Techniques10.1049/cdt2.1206217:3-4(180-194)Online publication date: 26-Jul-2023
  • (2023)Design of Digital Integrated Circuits by Improving the Characteristics of Digital CellsMachine Learning-based Design and Optimization of High-Speed Circuits10.1007/978-3-031-50714-4_6(279-336)Online publication date: 31-Dec-2023
  • (2022)Standard Cell Full Abutment Check Method2022 IEEE 41st International Conference on Electronics and Nanotechnology (ELNANO)10.1109/ELNANO54667.2022.9926993(47-50)Online publication date: 10-Oct-2022
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cover image ACM Conferences
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
March 2007
626 pages
ISBN:9781595936059
DOI:10.1145/1228784
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 March 2007

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Author Tags

  1. compact library
  2. digital design
  3. mutation algorithm
  4. standard-cell

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GLSVLSI07
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GLSVLSI07: Great Lakes Symposium on VLSI 2007
March 11 - 13, 2007
Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2023)Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flowIET Computers & Digital Techniques10.1049/cdt2.1206217:3-4(180-194)Online publication date: 26-Jul-2023
  • (2023)Design of Digital Integrated Circuits by Improving the Characteristics of Digital CellsMachine Learning-based Design and Optimization of High-Speed Circuits10.1007/978-3-031-50714-4_6(279-336)Online publication date: 31-Dec-2023
  • (2022)Standard Cell Full Abutment Check Method2022 IEEE 41st International Conference on Electronics and Nanotechnology (ELNANO)10.1109/ELNANO54667.2022.9926993(47-50)Online publication date: 10-Oct-2022
  • (2021)Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard CellsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2021.310923968:11(4660-4671)Online publication date: Nov-2021
  • (2020)From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern EnumerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288977239:2(520-532)Online publication date: Feb-2020
  • (2019)Efficiently Mapping VLSI Circuits With Simple CellsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281870938:4(692-704)Online publication date: Apr-2019
  • (2017)Virtual characterization for exhaustive DFM evaluation of logic cell libraries2017 18th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2017.7918299(93-98)Online publication date: Mar-2017
  • (2016)On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design2016 17th Latin-American Test Symposium (LATS)10.1109/LATW.2016.7483353(135-140)Online publication date: Apr-2016
  • (2014)Deriving Reduced Transistor Count Circuits from AIGsProceedings of the 27th Symposium on Integrated Circuits and Systems Design10.1145/2660540.2661008(1-7)Online publication date: 1-Sep-2014
  • (2011)A design methodology for the automatic sizing of standard-cell librariesProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973040(151-156)Online publication date: 2-May-2011
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