article

A critical-path-aware partial gating approach for test power reduction

Authors:

Mohammed Elshoukry,

Mohammad Tehranipoor,

C. P. RavikumarAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12, Issue 2

Pages 17 - es

https://doi.org/10.1145/1230800.1230809

Published: 01 April 2007 Publication History

Abstract

Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to block transitions propagating from the outputs of scan cells through combinational logic. In order to accomplish this, some researchers have proposed setting primary inputs to appropriate values or adding extra gates at the outputs of scan cells. In this article, we point out the limitations of such full gating techniques in terms of area overhead and performance degradation. We propose an alternate solution where a partial set of scan cells is gated. A subset of scan cells is selected to give maximum reduction in test power within a given area constraint. An alternate formulation of the problem is to treat maximum permitted test power as a constraint and achieve a test power that is within this limit using the fewest number of gated scan cells, thereby leading to the least impact in area overhead. Our problem formulation also comprehends performance constraints and prevents the inclusion of gating points on critical paths. The area overhead is predictable and closely corresponds to the average power reduction.

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Cited By

Naeini MDass SOoi C(2017)The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS TechnologyJournal of Low Power Electronics and Applications10.3390/jlpea70200077:2(7)Online publication date: 28-Apr-2017
https://doi.org/10.3390/jlpea7020007
Lee TYang J(2017)Physical-aware gating element insertion for thermal-safe scan shift operationIEICE Electronics Express10.1587/elex.14.2016118114:7(20161181-20161181)Online publication date: 2017
https://doi.org/10.1587/elex.14.20161181
Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
Show More Cited By

Index Terms

A critical-path-aware partial gating approach for test power reduction
1. Hardware
  1. Hardware test
  2. Robustness

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 12, Issue 2

April 2007

222 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1230800

Issue’s Table of Contents

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 2007

Published in TODAES Volume 12, Issue 2

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Cited By

Naeini MDass SOoi C(2017)The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS TechnologyJournal of Low Power Electronics and Applications10.3390/jlpea70200077:2(7)Online publication date: 28-Apr-2017
https://doi.org/10.3390/jlpea7020007
Lee TYang J(2017)Physical-aware gating element insertion for thermal-safe scan shift operationIEICE Electronics Express10.1587/elex.14.2016118114:7(20161181-20161181)Online publication date: 2017
https://doi.org/10.1587/elex.14.20161181
Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
Chung KKahng ALi J(2016)Comprehensive optimization of scan chain timing during late-stage IC implementationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897998(1-6)Online publication date: 5-Jun-2016
https://dl.acm.org/doi/10.1145/2897937.2897998
Naeini MOoi C(2015)A novel scan architecture for low power scan-based testingVLSI Design10.1155/2015/2640712015(3-3)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1155/2015/264071
Shuo Wang Tehranipoor M(2014)Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated CircuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.226381222:5(1030-1041)Online publication date: May-2014
https://doi.org/10.1109/TVLSI.2013.2263812
Zhao WMa JTehranipoor MChakravarty S(2013)Power-safe application of tdf patterns to flip-chip designs during wafer testACM Transactions on Design Automation of Electronic Systems10.1145/2491477.249148718:3(1-20)Online publication date: 29-Jul-2013
https://dl.acm.org/doi/10.1145/2491477.2491487
Lin YHuang JWen X(2012)A Transition Isolation Scan Cell Design for Low Shift and Capture PowerProceedings of the 2012 IEEE 21st Asian Test Symposium10.1109/ATS.2012.29(107-112)Online publication date: 19-Nov-2012
https://dl.acm.org/doi/10.1109/ATS.2012.29
Lin X(2011)Low Power Testing—What Can Commercial Design-for-Test Tools Provide?Journal of Low Power Electronics and Applications10.3390/jlpea10303571:3(357-372)Online publication date: 9-Dec-2011
https://doi.org/10.3390/jlpea1030357
Zhao WTehranipoor MChakravarty S(2011)Power-safe test application using an effective gating approach considering current limits29th VLSI Test Symposium10.1109/VTS.2011.5783777(160-165)Online publication date: May-2011
https://doi.org/10.1109/VTS.2011.5783777
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