Nobu Matsumoto
ABSTRACT
This paper describes a new datapath generator that generates high-density mask layouts equivalent to hand-crafted ones.
An entry of the generator is a hierarchical symbolic layout at the gate level. Bit-and-row-slicing technique is a key feature to realize large-size and high-density datapath generation. A 21K transistor datapath was generated using 1-μm CMOS technology, whose density is 5.64 KTr/mm2, greater than the 5.38 KTr/mm2 of a hand-crafted datapath.
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Index Terms
- Datapath generator based on gate-level symbolic layout
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