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An effective clustering algorithm for mixed-size placement

Published: 18 March 2007 Publication History

Abstract

Placement is a crucial step for the VLSI circuit physical design and it has a deep impact on the overall circuit performance. Numerous clustering techniques have been proposed and applied to placement to deal with the increasing circuit sizes and complexity. In this paper, an effective clustering algorithm for mixed-size placement is presented. This technique uses local cell connectivity information to identify all potential clusters, but finalizes clusters globally. The effectiveness of the proposed clustering technique is verified by empirical tests on ICCAD04 and ISPD05 benchmark circuits. Specifically, 4 major academic placers, including Capo10.1, FengShui5.1, mPL6 and NTUPlace3-LE, are tested by using the proposed clustering technique as a preprocessing step. The overall experimental results show that for ICCAD04 benchmarks, the proposed clustering technique consistently improves all of the placers' performance by 2% to 5% on average in term of the pin-to-pin half perimeter wire length, with comparable or lower runtime. For ISPD05 benchmarks, the proposed clustering technique shows promising results.

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Cited By

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  • (2017)Hierarchical and Analytical Placement Techniques for High-Performance Analog CircuitsProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036678(55-62)Online publication date: 19-Mar-2017
  • (2011)SafeChoiceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.211495030:7(1020-1033)Online publication date: 1-Jul-2011
  • (2010)SafeChoiceProceedings of the 19th international symposium on Physical design10.1145/1735023.1735066(185-192)Online publication date: 14-Mar-2010
  • Show More Cited By

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cover image ACM Conferences
ISPD '07: Proceedings of the 2007 international symposium on Physical design
March 2007
206 pages
ISBN:9781595936134
DOI:10.1145/1231996
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 March 2007

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Author Tags

  1. hypergraph clustering
  2. placement

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ISPD07
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ISPD07: International Symposium on Physical Design
March 18 - 21, 2007
Texas, Austin, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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International Symposium on Physical Design
March 16 - 19, 2025
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Cited By

View all
  • (2017)Hierarchical and Analytical Placement Techniques for High-Performance Analog CircuitsProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036678(55-62)Online publication date: 19-Mar-2017
  • (2011)SafeChoiceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.211495030:7(1020-1033)Online publication date: 1-Jul-2011
  • (2010)SafeChoiceProceedings of the 19th international symposium on Physical design10.1145/1735023.1735066(185-192)Online publication date: 14-Mar-2010
  • (2009)A Degree-Based Clustering Technique for VLSI PlacementJournal of Algorithms & Computational Technology10.1260/1748301087882517733:3(425-441)Online publication date: 1-Sep-2009
  • (2009)A study of routability estimation and clustering in placementProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687468(363-366)Online publication date: 2-Nov-2009
  • (2007)Clustering algorithms for circuit partitioning and placement problems2007 18th European Conference on Circuit Theory and Design10.1109/ECCTD.2007.4529654(547-550)Online publication date: Aug-2007

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