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Variability and yield improvement: rules, models, and characterization

Published: 05 November 2006 Publication History

Abstract

Yield and variability are becoming detractors for successful design in sub-90-nm process technologies. We consider the fundamental lithography and process issues that are driving variability and yield and the role of design rules in future processes. We examine the importance of layout-aware modeling and layout regularity, including advantages and cost. Characterization structures for examining the electrical effects of device-level variability are discussed as well as circuit techniques for mitigating variability and yield challenges.

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Cited By

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  • (2016)Surrogating circuit design solutions with robustness metricsIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.01552:C(1-9)Online publication date: 1-Jan-2016

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  1. Variability and yield improvement: rules, models, and characterization

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        cover image ACM Conferences
        ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
        November 2006
        147 pages
        ISBN:1595933891
        DOI:10.1145/1233501
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 05 November 2006

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        • (2016)Surrogating circuit design solutions with robustness metricsIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.01552:C(1-9)Online publication date: 1-Jan-2016

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