article

ASIP architecture exploration for efficient IPSec encryption: A case study

Authors:

Hanno Scharwaechter,

Andreas Wieferink,

Manuel Hohenauer,

Kingshuk Karuri,

Jianjiang Ceng,

Rainer Leupers,

Heinrich MeyrAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 6, Issue 2

Pages 12 - es

https://doi.org/10.1145/1234675.1234679

Published: 01 May 2007 Publication History

Abstract

Application-Specific Instruction-Set Processors (ASIPs) are becoming increasingly popular in the world of customized, application-driven System-on-Chip (SoC) designs. Efficient ASIP design requires an iterative architecture exploration loop---gradual refinement of the processor architecture starting from an initial template. To accomplish this task, design automation tools are used to detect bottlenecks in embedded applications, to implement application-specific processor instructions, and to automatically generate the required software tools (such as instruction-set simulator, C-compiler, assembler, and profiler), as well as to synthesize the hardware. This paper describes an architecture exploration loop for an ASIP coprocessor that implements common encryption functionality used in symmetric block cipher algorithms for internet protocol security (IPSec). The coprocessor is accessed via shared memory and, as a consequence, our approach is easily adaptable to arbitrary main processor architectures. This paper presents the extended version of our case study that has been already published on the SCOPES conference in 2004. In both papers, a MIPS architecture is used as the main processor and Blowfish as encryption algorithm.

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Cited By

Wang ZJia ZJu LChen R(2012)ASIP-based Design and Implementation of RSA for Embedded SystemsProceedings of the 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems10.1109/HPCC.2012.202(1375-1382)Online publication date: 25-Jun-2012
https://dl.acm.org/doi/10.1109/HPCC.2012.202
Li YJia ZChen R(2012)Towards a Dedicated ASIP for AES ImplementationMechanical Engineering and Technology10.1007/978-3-642-27329-2_60(441-444)Online publication date: 2012
https://doi.org/10.1007/978-3-642-27329-2_60
Chen RJia ZLi YXia HLi X(2011)The application specific instruction processor for AES2011 3rd International Conference on Electronics Computer Technology10.1109/ICECTECH.2011.5941928(394-396)Online publication date: Apr-2011
https://doi.org/10.1109/ICECTECH.2011.5941928
Show More Cited By

Index Terms

ASIP architecture exploration for efficient IPSec encryption: A case study
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 6, Issue 2

SPECIAL ISSUE SCOPES 2005

May 2007

119 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/1234675

Issue’s Table of Contents

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 May 2007

Published in TECS Volume 6, Issue 2

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Cited By

Wang ZJia ZJu LChen R(2012)ASIP-based Design and Implementation of RSA for Embedded SystemsProceedings of the 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems10.1109/HPCC.2012.202(1375-1382)Online publication date: 25-Jun-2012
https://dl.acm.org/doi/10.1109/HPCC.2012.202
Li YJia ZChen R(2012)Towards a Dedicated ASIP for AES ImplementationMechanical Engineering and Technology10.1007/978-3-642-27329-2_60(441-444)Online publication date: 2012
https://doi.org/10.1007/978-3-642-27329-2_60
Chen RJia ZLi YXia HLi X(2011)The application specific instruction processor for AES2011 3rd International Conference on Electronics Computer Technology10.1109/ICECTECH.2011.5941928(394-396)Online publication date: Apr-2011
https://doi.org/10.1109/ICECTECH.2011.5941928
Youn JLee JPaek YKim JCho JKathail VTatge RBarua R(2010)Implementing dynamic implied addressing mode for multi-output instructionsProceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1878921.1878937(87-96)Online publication date: 24-Oct-2010
https://dl.acm.org/doi/10.1145/1878921.1878937
Youn JAhn MPaek YKim JCho J(2010)Two versions of architectures for dynamic implied addressing modeJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2010.05.01456:8(368-383)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1016/j.sysarc.2010.05.014
Scharwaechter HYoun JLeupers RPaek YAscheid GMeyr HHa SChoi KDutt NTeich J(2007)A code-generator generator for multi-output instructionsProceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1289816.1289851(131-136)Online publication date: 30-Sep-2007
https://dl.acm.org/doi/10.1145/1289816.1289851
Karuri KAl Faruque MKraemer SLeupers RAscheid GMeyr HJoyner WMartin GKahng A(2005)Fine-grained application source code profiling for ASIP designProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065666(329-334)Online publication date: 13-Jun-2005
https://dl.acm.org/doi/10.1145/1065579.1065666

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