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A hardware/software framework for supporting transactional memory in a MPSoC environment

Authors:

Maurice HerlihyAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 35, Issue 1

Pages 47 - 54

https://doi.org/10.1145/1241601.1241611

Published: 01 March 2007 Publication History

Abstract

Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to provide increased concurrency, rather than increased clock speed, for both large-scale as well as embedded systems. Traditionally lock-based synchronization is provided to support concurrency; however, managing locks can be very difficult and error prone. In addition, the performance and power cost of lock-based synchronization can be high. Transactional memories have been extensively investigated as an alternative to lock-based synchronization in general-purpose systems. It has been shown that transactional memory has advantages over locks in terms of ease of programming, performance and energy consumption. However, their applicability to embedded multi-core platforms has not been explored yet. In this paper, we demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCore. Using cycle accurate power and performance models for the transactional memory hardware, we evaluate our architectural framework over a set of different system and application settings, and show that transactional memory is a promising solution, even for resource-constrained embedded multiprocessors.

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Cited By

Owda ZObermaisser R(2015)A Predictable Transactional Memory Architecture with Selective Conflict Resolution for Mixed-Criticality Support in MPSoCsProceedings of the 2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing (EUC)10.1109/EUC.2015.11(158-162)Online publication date: 21-Oct-2015
https://dl.acm.org/doi/10.1109/EUC.2015.11
Kim SLee SJun MLee BRo WChung EGaudiot J(2014)$C\!\!-\!\!Lock$IEEE Transactions on Computers10.1109/TC.2013.8463:8(1962-1974)Online publication date: 1-Aug-2014
https://dl.acm.org/doi/10.1109/TC.2013.84
Függer MSchmid U(2012)Reconciling fault-tolerant distributed computing and systems-on-chipDistributed Computing10.1007/s00446-011-0151-724:6(323-355)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1007/s00446-011-0151-7
Show More Cited By

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cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 35, Issue 1

March 2007

153 pages

ISSN:0163-5964

DOI:10.1145/1241601

Issue’s Table of Contents

Copyright © 2007 Authors.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 March 2007

Published in SIGARCH Volume 35, Issue 1

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Cited By

Owda ZObermaisser R(2015)A Predictable Transactional Memory Architecture with Selective Conflict Resolution for Mixed-Criticality Support in MPSoCsProceedings of the 2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing (EUC)10.1109/EUC.2015.11(158-162)Online publication date: 21-Oct-2015
https://dl.acm.org/doi/10.1109/EUC.2015.11
Kim SLee SJun MLee BRo WChung EGaudiot J(2014)$C\!\!-\!\!Lock$IEEE Transactions on Computers10.1109/TC.2013.8463:8(1962-1974)Online publication date: 1-Aug-2014
https://dl.acm.org/doi/10.1109/TC.2013.84
Függer MSchmid U(2012)Reconciling fault-tolerant distributed computing and systems-on-chipDistributed Computing10.1007/s00446-011-0151-724:6(323-355)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1007/s00446-011-0151-7
Moreira JKlein FBaldassin ACentoducatte PAzevedo RRigo S(2011)Using multiple abstraction levels to speedup an MPSoC virtual platform simulator2011 22nd IEEE International Symposium on Rapid System Prototyping10.1109/RSP.2011.5929982(99-105)Online publication date: May-2011
https://doi.org/10.1109/RSP.2011.5929982
Függer MDielacher ASchmid U(2010)How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via PipeliningProceedings of the 2010 European Dependable Computing Conference10.1109/EDCC.2010.35(230-239)Online publication date: 28-Apr-2010
https://dl.acm.org/doi/10.1109/EDCC.2010.35
Ferri CWood SMoreshet TIris Bahar RHerlihy M(2010)Embedded-TMJournal of Parallel and Distributed Computing10.1016/j.jpdc.2010.02.00370:10(1042-1052)Online publication date: 1-Oct-2010
https://dl.acm.org/doi/10.1016/j.jpdc.2010.02.003
Mankin JKaeli DArdini J(2009)Software transactional memory for multicore embedded systemsACM SIGPLAN Notices10.1145/1543136.154246544:7(90-98)Online publication date: 19-Jun-2009
https://dl.acm.org/doi/10.1145/1543136.1542465
Mankin JKaeli DArdini JKirsch CKandemir M(2009)Software transactional memory for multicore embedded systemsProceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1542452.1542465(90-98)Online publication date: 19-Jun-2009
https://dl.acm.org/doi/10.1145/1542452.1542465
Ferri CViescas AMoreshet TBahar RHerlihy MNarayanan VYan ZMacii EBhanja S(2008)Energy efficient synchronization techniques for embedded architecturesProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366213(435-440)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366213

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