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Fuce: the continuation-based multithreading processor

Published: 07 May 2007 Publication History

Abstract

Current trends of research on multithreading processors are the chip multithreading (CMT), which aims to exploit thread level parallelism (TLP) and to improve performance of software built onalltraditional threading components, e.g. pthreads. However, CMT is principally a straight forward extension of conventionalall symmetric multiprocessor (SMP) techniques, and it will suffer from the same limits to scalable multithreaded processing ifallit is built only on the traditional sequential-computation-based framework. Consideringallthese limitations of sequential-processor-basedallmultithreading, we are taking another approach to developing a multithreading processor dedicated to thread level parallelism(TLP). Our processor, named Fuce, is based on continuation-based multithreading. A thread is defined as a block of sequentially ordered instructions which areall executed exclusively. Every execution of a thread is triggered by one or more events, each of which is called continuation. The hardware cost and performance of the Fuce processor areallevaluated by means of a hardware implementation on FPGA and software simulation.

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Cited By

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  • (2018)A continuation-based noninterruptible multithreading processor architectureThe Journal of Supercomputing10.1007/s11227-008-0246-547:2(228-252)Online publication date: 30-Dec-2018
  • (2015)Paradigm Shift for EXASCALE ComputingProceedings of the 3rd International Conference on Exascale Applications and Software10.5555/2820083.2820104(109-114)Online publication date: 21-Apr-2015
  • (2011)Data-triggered threads: Eliminating redundant computation2011 IEEE 17th International Symposium on High Performance Computer Architecture10.1109/HPCA.2011.5749727(181-192)Online publication date: Feb-2011
  • Show More Cited By

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cover image ACM Conferences
CF '07: Proceedings of the 4th international conference on Computing frontiers
May 2007
300 pages
ISBN:9781595936837
DOI:10.1145/1242531
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 07 May 2007

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Author Tags

  1. chip multi-processor
  2. continuation-based multithread programming
  3. multithreading
  4. thread-level parallelism

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CF07: Computing Frontiers Conference
May 7 - 9, 2007
Ischia, Italy

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Overall Acceptance Rate 273 of 785 submissions, 35%

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Cited By

View all
  • (2018)A continuation-based noninterruptible multithreading processor architectureThe Journal of Supercomputing10.1007/s11227-008-0246-547:2(228-252)Online publication date: 30-Dec-2018
  • (2015)Paradigm Shift for EXASCALE ComputingProceedings of the 3rd International Conference on Exascale Applications and Software10.5555/2820083.2820104(109-114)Online publication date: 21-Apr-2015
  • (2011)Data-triggered threads: Eliminating redundant computation2011 IEEE 17th International Symposium on High Performance Computer Architecture10.1109/HPCA.2011.5749727(181-192)Online publication date: Feb-2011
  • (2007)Scalability of continuation-based fine-grained multithreading in handling multiple I/O requests on FUCEProceedings of the 4th international conference on Computing frontiers10.1145/1242531.1242564(225-236)Online publication date: 7-May-2007

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