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Interface synthesis for heterogeneous multi-core systems from transaction level models

Published: 13 June 2007 Publication History

Abstract

This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters in the platform and generates interface modules called universal bridges between buses in the design. The design and configuration of the bridges depend on several platform components including heterogeneity of the components, traffic on the bus, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the bridge can be automatically derived based on these parameters. We use industrial strength design drivers such as an MP3 decoder to test our automatically generated bridges for a variety of platforms and compare them to manually designed bridges on different quality metrics. Our experimental results show that performance of automatically generated bridges are within 5% of manual design for simple platforms but surpasses them for more complex platforms. The area and RTL code size is consistently better than manual design while giving 5 orders of improvement in development time.

References

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G. Borriello, L. Lavagno, and R. B. Ortega, "Interface synthesis: a vertical slice from digital logic to software components", In Proc. of ICCAD, 1998
[2]
S. Narayan and D. Gajski, "Synthesis os system-level bus interfaces.", Proc. European Design and Test Conference, 1997 Pages 395--399
[3]
Passerone, R., Rowson, J., Sangiovanni-Vincentelli, A., "Automatic Synthesis of Interfaces between Incompatible Protocols", Proc. 35th Design Automation Conf. (DAC 98), ACM Press, San Francisco, CA, 1998.
[4]
Yin-Tsung Hwang; Sung-Chun Lin, "Automatic protocol translation and template based interface synthesis for IP reuse in SoC", The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. pages 565--568
[5]
L. Benini, G. De Micheli, "Networks on Chips: A New Soc Paradigm", IEEE Computer, vol.35, January 2002 pages 70--78

Cited By

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  • (2015)Automatic communication-driven virtual prototyping and design for networked embedded systemsMicroprocessors & Microsystems10.1016/j.micpro.2015.08.00839:8(1012-1028)Online publication date: 1-Nov-2015
  • (2014)An IP interface design compiler with SystemC based input specifications2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2014.6934005(149-152)Online publication date: Jun-2014
  • (2012)Synthesis of optimized hardware transactors from abstract communication specificationsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380508(403-412)Online publication date: 7-Oct-2012
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  1. Interface synthesis for heterogeneous multi-core systems from transaction level models

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      cover image ACM Conferences
      LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
      June 2007
      258 pages
      ISBN:9781595936325
      DOI:10.1145/1254766
      • cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 42, Issue 7
        Proceedings of the 2007 LCTES conference
        July 2007
        241 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/1273444
        Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      New York, NY, United States

      Publication History

      Published: 13 June 2007

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      Author Tags

      1. HW-SW co-design
      2. channel
      3. communication synthesis
      4. interface synthesis
      5. transaction level model
      6. universal bridge

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      Cited By

      View all
      • (2015)Automatic communication-driven virtual prototyping and design for networked embedded systemsMicroprocessors & Microsystems10.1016/j.micpro.2015.08.00839:8(1012-1028)Online publication date: 1-Nov-2015
      • (2014)An IP interface design compiler with SystemC based input specifications2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2014.6934005(149-152)Online publication date: Jun-2014
      • (2012)Synthesis of optimized hardware transactors from abstract communication specificationsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380508(403-412)Online publication date: 7-Oct-2012
      • (2010)Embedded system environment: A framework for TLM-based design and prototypingProceedings of 2010 21st IEEE International Symposium on Rapid System Protyping10.1109/RSP.2010.5656342(1-7)Online publication date: Jun-2010
      • (2010)Hardware design methodology to synthesize communication interfaces from TLM to RTLProceedings of the 2010 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR) - Volume 0210.1109/AQTR.2010.5520832(1-5)Online publication date: 28-May-2010
      • (2014)Communication-Driven Automatic Virtual Prototyping for Networked Embedded SystemsProceedings of the 2014 17th Euromicro Conference on Digital System Design10.1109/DSD.2014.88(435-442)Online publication date: 27-Aug-2014
      • (2009)Automatic IP Interface Synthesis Supporting Multi-layer Communication Protocols in SoC DesignsProceedings of the 2009 Fifth International Conference on Information Assurance and Security - Volume 0110.1109/IAS.2009.270(169-172)Online publication date: 18-Aug-2009
      • (2008)HW/SW Auto-Coupling for Fast IP Integration in SoC DesignsProceedings of the 2008 International Conference on Embedded Software and Systems10.1109/ICESS.2008.91(556-563)Online publication date: 29-Jul-2008

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