article

Temporal floorplanning using the three-dimensional transitive closure subGraph

Authors:

Yao-Wen ChangAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12, Issue 4

Pages 37 - es

https://doi.org/10.1145/1278349.1278350

Published: 01 September 2007 Publication History

Abstract

Improving logic capacity by time-sharing, dynamically reconfigurable Field Gate Programmable Arrays (FPGAs) are employed to handle designs of high complexity and functionality. In this paper, we use a novel graph-based topological floorplan representation, named 3D-subTCG (3-Dimensional Transitive Closure subGraph), to deal with the 3-dimensional (temporal) floorplanning/placement problem, arising from dynamically reconfigurable FPGAs. The 3D-subTCG uses three transitive closure graphs to model the temporal and spatial relations between modules. We derive the feasibility conditions for the precedence constraints induced by the execution of the dynamically reconfigurable FPGAs. Because the geometric relationship is transparent to the 3D-subTCG and its induced operations (i.e., we can directly detect the relationship between any two tasks from the representation), we can easily detect any violation of the temporal precedence constraints on 3D-subTCG. We also derive important properties of the 3D-subTCG to reduce the solution space and shorten the running time for 3D (temporal) foorplanning/placement. Experimental results show that our 3D-subTCG-based algorithm is very effective and efficient.

References

[1]

Adya, S. N. and Markov, I. L. 2001. Fixed-outline floorplanning through better local search. In Proceedings of IEEE International Conference of Computer Design. 328--334.

Digital Library

[2]

Adya, S. N. and Markov, I. L. 2003. Fixed-outline floorplanning: Enabling hierarchical design. IEEE Trans Very Large Scale Integra. Syst. 11, 6 (Dec.), 1120--1135.

Digital Library

[3]

Alsolaim, A., Becker, J., Glesner, M., and Starzyk, J. 2000. Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines. 205--214.

Digital Library

[4]

Atmel. 1997. AT6000 FPGA Configuration Guide Documentation 0436B. Atmel, Inc.

[5]

Banerjee, S., Bozorgzadeh, E., and Dutt, N. 2005. Hw-sw partitioning for architectures with partial dynamic reconfiguration. Tech. rep. CECS-TR-05-02, UC Irvine.

[6]

Bazargan, K., Kastner, R., and Sarrafzadeh, M. 2000a. 3-d floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems. Design Autom. for Embed. Syst.---RSP'99 Special Issue.

Digital Library

[7]

Bazargan, K., Kastner, R., and Sarrafzadeh, M. 2000b. Fast template placement for reconfigurable computing systems. IEEE Design Test Comput. 17, 1 (March), 68--83.

Digital Library

[8]

Bazargan, K. and Sarrafzadeh, M. 1999. Fast online placement for reconfigurable computing systems. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines. 300--302.

Digital Library

[9]

Chaubal, A. P. 2004. Design and implementation of an FPGA-based partially reconfigurable network controller. Master thesis, Virginia Polytechnic Institute and State University.

[10]

Cooly, J. M. and Tukey, J. W. 1965. An algorithm for the machine calculation of complex fourier series. Math. Comput. 19, 297--301.

[11]

Durbano, J. P. and Ortiz, F. E. 2004. FPGA-based acceleration of the 3d finite-difference time-domain method. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines. 156--163.

Digital Library

[12]

Fekete, S. P., Kohler, E., and Teich, J. 2001. Optimal FPGA module placement with temporal precedence constraints. In Proceedings of Design Automation and Test in Europe. 658--665.

Digital Library

[13]

Fekete, S. P. and Schepers, J. 1997. On more-dimensional packing iii: Exact algorithms. ZPR Tech. Rep. 97-290.

[14]

Ghiasi, S. and Sarrafzadeh, M. 2003. Optimal reconfiguration sequence management. In Proceedings of Asia-South Pacific Design Automation Conference. 359--365.

Digital Library

[15]

Hauck, S. 1998. The roles of FPGAs in reprogrammable systems. Proceedings of IEEE 86, 4 (April), 615--639.

[16]

Hauck, S., Li, Z., and Schwabe, E. 1998. Configuration compression for the Xilinx xc6200 FPGA. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines. 138--146.

Digital Library

[17]

He, C., Lu, M., and Sun, C. 2004. Accelerating seismic migration using FPGA-based coprocessor platform. In Proc. FCCM. 207--216.

Digital Library

[18]

Hudson, R., Lehn, D., and Athanas, P. 1998. A runtime reconfigurable engine for image interpolation. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines. 88--95.

Digital Library

[19]

Kahng, A. B. 2000. Classical floorplanning harmful&quest; In Proceedings of the International Symposium on Physical Design. 207--213.

Digital Library

[20]

Kaneko, M., Yokoyama, J., and Tayu, S. 2002. 3d scheduling based on code space exploration for dynamically reconfigurable systems. In Proc. of ISCAS. Vol. 5, 465--468.

[21]

Kirkpatrick, S., Gelatt, C. D., and Vecchi, M. P. 1983. Optimization by simulated annealing. Science 220, 4598 (May), 671--680.

[22]

Lawler, E. 1976. Combinatorial Optimization: Networks and Matroids. Holt, Rinehart, and Winston.

[23]

Lin, J.-M. and Chang, Y.-W. 2001. Tcg: A transitive closure graph-based representation for non-slicing floorplans. In Proceedings of Design Automation Conference. 764--769.

Digital Library

[24]

Luk, W., Shirazi, N., and Cheung, P. Y. K. 1997. Compilation tools for runtime reconfigurable designs. In Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines. 56--65.

Digital Library

[25]

Murata, H., Fujiyoshi, K., Nakatake, S., and Kajitani, Y. 1995. Rectangle-packing based module placement. In Proceedings of International Conference on Computer-Aided Design. 472--479.

Digital Library

[26]

Papachristou, C. A. and Konuk, H. 1990. A linear program drive scheduling and allocation method followed by interconnect optimization algorithm. In Proceedings of Design Automation Conference. 77--83.

Digital Library

[27]

picochip. http://www.picochip.com/.

[28]

quicksilver. http://www.qstech.com/products.htm.

[29]

Shoa, A. and Shirani, S. 2005. Run-time reconfigurable systems for digital signal processing applications: A survey. J. VLSI Signal Proc. 39, 3 (March), 213--235.

Digital Library

[30]

Swaminathan, S., Tessier, R., Goeckel, D., and Burleson, W. 2002. A dynamically reconfigurable adaptive viterbi decoder. In Proceedings of the 10th International Symposium on Field Programmable Gate Arrays. 227--236.

Digital Library

[31]

Teich, J., Fekete, S. P., and Schepers, J. 1999. Compile-time optimization of dynamic hardware reconfigurations. In Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications. 1097--1103.

[32]

Tessier, R. and Burleson, W. 2001. Reconfigurable computing for digital signal processing: A survey. J. VLSI Siganl Proc. 28, 1 (May/June), 7--27.

Digital Library

[33]

TORSCHE. TORSCHE Scheduling Toolbox for Matlab User's Guide v0.2.0b2.

[34]

Wu, G.-M., Lin, J.-M., and Chang, Y.-W. 2001. An algorithm for dynamically reconfigurable fpga placement. In Proceedings of International Conference on Computer Design. 501--504.

Digital Library

[35]

Xilinx. http://www.xilinx.com/prs_rls/prs_rls2001.htm.

[36]

Xilinx. 1996. XC6200 Field Programmable Gate Arrays Data Sheet. Xilinx, Inc.

[37]

Xilinx. 2000. XAPP151 Virtex Series Configuration Architecture User Guide v1.5. Xilinx, Inc.

[38]

Yamazaki, H., Sakanushi, K., Nakatake, S., and Kajitani, Y. 2000. 3d-packing by metadata structure and packing heuristics. E83-A, 4 (April), 639--645.

[39]

Yuh, P.-H., Yang, C.-L., and Chang, Y.-W. 2004. Temporal floorplanning using the t-tree formulation. In Proceedings of International Conference on Computer-Aided Design. 300--305.

Digital Library

Cited By

Ding BHuang JWang JXu QChen SKang Y(2023)Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous ResourcesACM Transactions on Design Automation of Electronic Systems10.1145/362529528:6(1-26)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3625295
Chen SHuang JXu XDing BXu Q(2019)Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288398239:1(199-212)Online publication date: 20-Dec-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2883982
Das SKim D(2019)A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design20th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2019.8697605(323-328)Online publication date: Mar-2019
https://doi.org/10.1109/ISQED.2019.8697605
Show More Cited By

Index Terms

Temporal floorplanning using the three-dimensional transitive closure subGraph
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 12, Issue 4

September 2007

449 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1278349

Issue’s Table of Contents

Copyright © 2007 ACM.

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 September 2007

Published in TODAES Volume 12, Issue 4

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Cited By

Ding BHuang JWang JXu QChen SKang Y(2023)Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous ResourcesACM Transactions on Design Automation of Electronic Systems10.1145/362529528:6(1-26)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3625295
Chen SHuang JXu XDing BXu Q(2019)Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288398239:1(199-212)Online publication date: 20-Dec-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2883982
Das SKim D(2019)A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design20th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2019.8697605(323-328)Online publication date: Mar-2019
https://doi.org/10.1109/ISQED.2019.8697605
Kang IQiao FPark DKane DYoung ECheng CGraham R(2018)Three-dimensional Floorplan Representations by Using Corner Links and Partial OrderACM Transactions on Design Automation of Electronic Systems10.1145/328917924:1(1-33)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1145/3289179
Rabozzi MDurelli GMiele ALillis JSantambrogio M(2017)Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements GenerationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.256236125:1(151-164)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2562361
Qiao FKang IKane DYoung FCheng CGraham R(2016)3D floorplan representations: Corner links and partial order2016 IEEE International 3D Systems Integration Conference (3DIC)10.1109/3DIC.2016.7970023(1-5)Online publication date: Nov-2016
https://doi.org/10.1109/3DIC.2016.7970023
Rabozzi MMiele ASantambrogio M(2015)Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements DetectionProceedings of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2015.16(252-255)Online publication date: 2-May-2015
https://dl.acm.org/doi/10.1109/FCCM.2015.16
Rabozzi MLillis JSantambrogio M(2014)Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines10.1109/FCCM.2014.61(186-193)Online publication date: May-2014
https://doi.org/10.1109/FCCM.2014.61
LIU NCHEN SYOSHIMURA T(2013)Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAsIEICE Transactions on Electronics10.1587/transele.E96.C.501E96.C:4(501-510)Online publication date: 2013
https://doi.org/10.1587/transele.E96.C.501
Wold AKoch DTorresen J(2013)Component based design using constraint programming for module placement on FPGAs2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2013.6581541(1-8)Online publication date: Jul-2013
https://doi.org/10.1109/ReCoSoC.2013.6581541
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