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Low-Power and testable circuit synthesis using Shannon decomposition

Published: 01 September 2007 Publication History

Abstract

Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance can result in improved test cost and test confidence. In this article, we analyze the testability in a new style of logic design based on Shannon's decomposition and supply gating. We observe that the tree structure of a logic circuit due to Shannon's decomposition makes it intrinsically more testable than a conventionally synthesized circuit, while at the same time providing an improvement in active power. We have analyzed four different aspects of the testability of a circuit: a) IDDQ test sensitivity, b) test power during scan-based testing, c) test length (for both ATPG-generated deterministic and random patterns), and d) noise immunity. Simulation results on a set of MCNC benchmarks show promising results on all these aspects (an average improvement of 94% in IDDQ sensitivity, 50% in test power, 19% (21%) in test length for deterministic (random) patterns, and 50% in coupling noise immunity). We have also demonstrated that the new logic structure can improve parametric yield (6% on average) of a circuit under process variations when considering a bound on circuit leakage.

References

[1]
Bhunia, S., Banerjee, N., Chen, Q., and Roy, H. M. K. 2005. A novel synthesis approach for active leakage power reduction using dynamic supply gating. Design Automation Conference.
[2]
Brglez, F. 1984. On testability of combinational networks. In Proceedings of the IEEE International Symposium on Compound Semiconductors. 221--225.
[3]
Bushnell, M. L. and Agarwal, V. D. 2000. Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI Circuits. Kluwer.
[4]
Ghosh, S., Bhunia, S., and Roy, K. 2005. Shannon expansion based supply-gated logic for improved power and testability. Asian Test Symposium. 404--409.
[5]
Kundu, S. 2000. Test challenges in nanometer technologies. European Test Workshop. 83--90.
[6]
Lavagno, L., McGeer, P., Saldanha, A., and Sangiovanni-Vincentelli, A. 1995. Timed Shannon circuits: A power-efficient design style and synthesis tool. Design Automation Conference. 254--260.

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      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 12, Issue 4
      September 2007
      449 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/1278349
      Issue’s Table of Contents

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      Association for Computing Machinery

      New York, NY, United States

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      Publication History

      Published: 01 September 2007
      Published in TODAES Volume 12, Issue 4

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      Author Tags

      1. Design-for-test
      2. IDDQ
      3. Shannon expansion
      4. dynamic supply gating
      5. noise immunity
      6. test coverage
      7. test power

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