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Chip multi-processor generator

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Mark HorowitzAuthors Info & Claims

DAC '07: Proceedings of the 44th annual Design Automation Conference

Pages 262 - 263

https://doi.org/10.1145/1278480.1278544

Published: 04 June 2007 Publication History

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Abstract

The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, universal computing platform that will supersede the microprocessor. We argue that these flexible, general computing chips are trying to accomplish more than is commercially needed. Since design NRE costs are an order of magnitude larger than fabrication NRE costs, a two-step design system seems attractive. First, the users configure/program a flexible computing framework to run their application with the desired performance. Then, the system "compiles" the program and configuration, tailoring the original framework to create a chip that is optimized toward the desired set of applications. Thus the user gets the reduced development costs of using a flexible solution with the efficiency of a custom chip.

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Cited By

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Khazraee MZhang LVega LTaylor M(2017)MoonwalkACM SIGARCH Computer Architecture News10.1145/3093337.303774945:1(511-526)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093337.3037749
Khazraee MZhang LVega LTaylor M(2017)MoonwalkACM SIGPLAN Notices10.1145/3093336.303774952:4(511-526)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093336.3037749
Khazraee MZhang LVega LTaylor M(2017)MoonwalkACM SIGOPS Operating Systems Review10.1145/3093315.303774951:2(511-526)Online publication date: 4-Apr-2017
https://doi.org/10.1145/3093315.3037749
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Index Terms

Chip multi-processor generator
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

DAC '07: Proceedings of the 44th annual Design Automation Conference

June 2007

1016 pages

ISBN:9781595936271

DOI:10.1145/1278480

General Chair:
Steven P. Levitan
Univ. of Pittsburgh, Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 04 June 2007

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SIGDA

DAC07: The 44th Annual Design Automation Conference 2007

June 4 - 8, 2007

California, San Diego

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DAC '07 Paper Acceptance Rate 152 of 659 submissions, 23%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Khazraee MZhang LVega LTaylor M(2017)MoonwalkACM SIGARCH Computer Architecture News10.1145/3093337.303774945:1(511-526)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093337.3037749
Khazraee MZhang LVega LTaylor M(2017)MoonwalkACM SIGPLAN Notices10.1145/3093336.303774952:4(511-526)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093336.3037749
Khazraee MZhang LVega LTaylor M(2017)MoonwalkACM SIGOPS Operating Systems Review10.1145/3093315.303774951:2(511-526)Online publication date: 4-Apr-2017
https://doi.org/10.1145/3093315.3037749
Khazraee MZhang LVega LTaylor MChen YTemam OCarter J(2017)MoonwalkProceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3037697.3037749(511-526)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3037697.3037749
Chen YCong JGill MReinman GXiao B(2015)Customizable ComputingSynthesis Lectures on Computer Architecture10.2200/S00650ED1V01Y201505CAC03310:3(1-118)Online publication date: 6-Jul-2015
https://doi.org/10.2200/S00650ED1V01Y201505CAC033
Qadeer WHameed RShacham OVenkatesan PKozyrakis CHorowitz M(2013)Convolution engineACM SIGARCH Computer Architecture News10.1145/2508148.248592541:3(24-35)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2508148.2485925
Qadeer WHameed RShacham OVenkatesan PKozyrakis CHorowitz MMendelson A(2013)Convolution engineProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485925(24-35)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2485922.2485925
Zhu QBerger CTurner EPileggi LFranchetti F(2013)Local Interpolation-based Polar Format SARJournal of Signal Processing Systems10.1007/s11265-012-0720-471:3(297-312)Online publication date: 1-Jun-2013
https://dl.acm.org/doi/10.1007/s11265-012-0720-4
Owaida MBellas NAntonopoulos CDaloukas KAntoniadis CPhillips JHu AGraeb H(2011)Massively parallel programming models used as hardware description languagesProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132409(326-333)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132409
Owaida MBellas NAntonopoulos CDaloukas KAntoniadis C(2011)Massively parallel programming models used as hardware description languagesProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105349(326-333)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.1109/ICCAD.2011.6105349
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Recommendations

Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip

An integrated high-level hardware/software partitioning methodology

Toward on-chip datacenters: a perspective on general trends and on-chip particulars

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