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Transition delay fault test pattern generation considering supply voltage noise in a SOC design

Published: 04 June 2007 Publication History

Abstract

Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise is increasing. The supply noise is much larger during at-speed delay test compared to normal circuit operation since large number of transitions occur within a short time frame. Existing commercial ATPG tools do not consider the excessive supply noise that might occur in the design during test pattern generation. In this paper, we first present a case study of a SOC design and show detailed IR-drop analysis, measurement and its effects on design performance during at-speed test. We then propose a novel method to measure the average power of at-speed test patterns, referred to as switching cycle average power (SCAP). A new practical pattern generation methodology is proposed to generate supply noise tolerant delay test patterns using existing capabilities in commercial ATPG tools. The results demonstrate that the new patterns generated using our technique will minimize the supply noise effects on path delay.

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  • (2017)A Low Capture Power Test Generation Method Based on Capture Safe Test Vector ManipulationIEICE Transactions on Information and Systems10.1587/transinf.2016EDP7418E100.D:9(2118-2125)Online publication date: 2017
  • (2016)Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test2016 IEEE 25th Asian Test Symposium (ATS)10.1109/ATS.2016.49(19-24)Online publication date: Nov-2016
  • (2015)Harzard-Based ATPG for Improving Delay Test QualityJournal of Electronic Testing: Theory and Applications10.1007/s10836-014-5503-331:1(27-34)Online publication date: 1-Feb-2015
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  1. Transition delay fault test pattern generation considering supply voltage noise in a SOC design

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      cover image ACM Conferences
      DAC '07: Proceedings of the 44th annual Design Automation Conference
      June 2007
      1016 pages
      ISBN:9781595936271
      DOI:10.1145/1278480
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 04 June 2007

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      Author Tags

      1. delay testing
      2. supply noise
      3. test generation

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      Cited By

      View all
      • (2017)A Low Capture Power Test Generation Method Based on Capture Safe Test Vector ManipulationIEICE Transactions on Information and Systems10.1587/transinf.2016EDP7418E100.D:9(2118-2125)Online publication date: 2017
      • (2016)Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test2016 IEEE 25th Asian Test Symposium (ATS)10.1109/ATS.2016.49(19-24)Online publication date: Nov-2016
      • (2015)Harzard-Based ATPG for Improving Delay Test QualityJournal of Electronic Testing: Theory and Applications10.1007/s10836-014-5503-331:1(27-34)Online publication date: 1-Feb-2015
      • (2014)Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based TestingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228228133:1(127-138)Online publication date: 1-Jan-2014
      • (2013)A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan TestingIEICE Transactions on Information and Systems10.1587/transinf.E96.D.2003E96.D:9(2003-2011)Online publication date: 2013
      • (2013)Power-safe application of tdf patterns to flip-chip designs during wafer testACM Transactions on Design Automation of Electronic Systems10.1145/2491477.249148718:3(1-20)Online publication date: 29-Jul-2013
      • (2013)A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)10.1109/ETS.2013.6569356(1-6)Online publication date: May-2013
      • (2013)Worst-Case Critical-Path Delay Analysis Considering Power-Supply NoiseProceedings of the 2013 22nd Asian Test Symposium10.1109/ATS.2013.17(37-42)Online publication date: 18-Nov-2013
      • (2012)A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits2012 IEEE 30th VLSI Test Symposium (VTS)10.1109/VTS.2012.6231102(197-202)Online publication date: Apr-2012
      • (2012)A Transition Isolation Scan Cell Design for Low Shift and Capture PowerProceedings of the 2012 IEEE 21st Asian Test Symposium10.1109/ATS.2012.29(107-112)Online publication date: 19-Nov-2012
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