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RISPP: rotating instruction set processing platform

Published: 04 June 2007 Publication History

Abstract

Adaptation in embedded processing is key in order to address efficiency. The concept of extensible embedded processors works well if a few a-priori known hot spots exist. However, they are far less efficient if many and possible at-design-time-unknown hot spots need to be dealt with. Our RISPP approach advances the extensible processor concept by providing flexibility through runtime adaptation by what we call "instruction rotation". It allows sharing resources in a highly flexible scheme of compatible components (called Atoms and Molecules). As a result, we achieve high speed-ups at moderate additional hardware. Furthermore, we can dynamically tradeoff between area and speed-up through runtime adaptation. We present the main components of our platform and discuss by means of an H.264 video codec.

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  • (2020)HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework2020 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC50251.2020.00011(13-24)Online publication date: Oct-2020
  • (2018)StitchProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00054(575-587)Online publication date: 2-Jun-2018
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      cover image ACM Conferences
      DAC '07: Proceedings of the 44th annual Design Automation Conference
      June 2007
      1016 pages
      ISBN:9781595936271
      DOI:10.1145/1278480
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 04 June 2007

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      Author Tags

      1. ASIP
      2. extensible embedded processors
      3. reconfigurable computing
      4. run-time adaptation

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      DAC '07 Paper Acceptance Rate 152 of 659 submissions, 23%;
      Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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      Cited By

      View all
      • (2022)MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memoryACM Journal on Emerging Technologies in Computing Systems10.1145/348582418:3(1-24)Online publication date: 29-Jan-2022
      • (2020)HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework2020 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC50251.2020.00011(13-24)Online publication date: Oct-2020
      • (2018)StitchProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00054(575-587)Online publication date: 2-Jun-2018
      • (2017)Timing Analysis of Tasks on Runtime Reconfigurable ProcessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.257230425:1(294-307)Online publication date: 1-Jan-2017
      • (2017)Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2017.8124946(1-6)Online publication date: Oct-2017
      • (2017)Application-Specific ProcessorsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_13-1(1-33)Online publication date: 8-Apr-2017
      • (2017)Application-Specific ProcessorsHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_13(377-409)Online publication date: 27-Sep-2017
      • (2015)Feasibility of high level compiler optimizations in online synthesis2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2015.7393310(1-7)Online publication date: Dec-2015
      • (2014)Exploiting FPGA-Aware Merging of Custom Instructions for Runtime ReconfigurationACM Transactions on Reconfigurable Technology and Systems10.1145/26552407:3(1-15)Online publication date: 3-Sep-2014
      • (2014)Adaptive Energy Management for Dynamically Reconfigurable ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228226533:1(50-63)Online publication date: 1-Jan-2014
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