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Gate sizing for cell library-based designs

Published: 04 June 2007 Publication History

Abstract

With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shift, the problem of discrete gate sizing has received significantly less attention than its continuous counterpart. On the other hand, cell sizes of many realistic libraries are sparse, for example, geometrically spaced, which makes the nearest rounding approach inapplicable as large timing violations may be introduced. Therefore, it is highly desirable to design an effective algorithm to handle this discrete gate sizing problem.
Such an algorithm is proposed in this paper. The algorithm is a continuous solution guided dynamic programming approach. A set of novel techniques, such as Locality Sensitive Hashing based solution selection and stage pruning, are also proposed to accelerate the algorithm and improve the solution quality. Our experimental results demonstrate that (1) nearest rounding approach often leads to large timing violations and (2) compared to the well-known Coudert's approach, the new algorithm saves 9% -- 31% in area cost while still satisfying the timing constraint.

References

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C.-P. Chen, C. Chu, and D. Wong, "Fast and exact simultaneous gate and wire sizing by lagrangian relaxation," TCAD, vol. 18, no. 7, pp. 1014--1025, 1999.
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O. Coudert, "Gate sizing for constrained delay/power/area optimization," TVLSI, vol. 5, no. 4, pp. 465--472, 1997.
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W. Chuang, S. Sapatnekar, and I. Hajj, "Delay and area optimization for discrete gate sizes under double-sided timing constraints," CICC, 1993.
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F. Beeftink, P. Kudva, D. Kung, and L. Stok, "Gate-size selection for standard cell libraries," in ICCAD, pp. 545--550, 1998.
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A. Gionis, P. Indyk, and R. Motwani, "Similarity search in high dimensions via hashing," in Proceedings of ACM International Conference on Very Large Data Bases (VLDB), pp. 518--529, 1999.
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K. Kasamasetty, M. Ketkar, and S. S. Sapatnekar, "A new class of convex functions for delay modeling and its application to the transistor sizing problem," TCAD, vol. 19, no. 7, pp. 779--788, 2000.
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Cited By

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  • (2023)DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI GraphsACM Transactions on Design Automation of Electronic Systems10.1145/357701928:4(1-31)Online publication date: 17-May-2023
  • (2019)Fast Lagrangian Relaxation Based Multi-Threaded Gate Sizing Using Simple Timing CalibrationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.2915324(1-1)Online publication date: 2019
  • (2015)Fast Lagrangian Relaxation Based Gate Sizing using Multi-ThreadingProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840879(426-433)Online publication date: 2-Nov-2015
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    cover image ACM Conferences
    DAC '07: Proceedings of the 44th annual Design Automation Conference
    June 2007
    1016 pages
    ISBN:9781595936271
    DOI:10.1145/1278480
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 04 June 2007

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    Author Tags

    1. dynamic programming
    2. gate sizing

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    DAC '07 Paper Acceptance Rate 152 of 659 submissions, 23%;
    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

    View all
    • (2023)DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI GraphsACM Transactions on Design Automation of Electronic Systems10.1145/357701928:4(1-31)Online publication date: 17-May-2023
    • (2019)Fast Lagrangian Relaxation Based Multi-Threaded Gate Sizing Using Simple Timing CalibrationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.2915324(1-1)Online publication date: 2019
    • (2015)Fast Lagrangian Relaxation Based Gate Sizing using Multi-ThreadingProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840879(426-433)Online publication date: 2-Nov-2015
    • (2013)Fast and efficient lagrangian relaxation-based discrete gate sizingProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485725(1855-1860)Online publication date: 18-Mar-2013
    • (2013)Fast and near-optimal timing-driven cell sizing under cell area and leakage power constraints using a simplified discrete network flow algorithmVLSI Design10.1155/2013/4746012013(1-1)Online publication date: 1-Jan-2013
    • (2013)Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)10.1109/ISCAS.2013.6572398(2549-2552)Online publication date: May-2013
    • (2012)Simultaneous clock and data gate sizing algorithm with common global objectiveProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160948(145-152)Online publication date: 25-Mar-2012
    • (2012)Accelerating Gate Sizing Using Graphics Processing UnitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216453931:1(160-164)Online publication date: 1-Jan-2012
    • (2012)Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS)10.1109/LASCAS.2012.6180359(1-4)Online publication date: Feb-2012
    • (2012)Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)10.1109/ICECS.2012.6463706(468-471)Online publication date: Dec-2012
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