Article

Clock period minimization with minimum delay insertion

Authors:

Shih-Hsu Huang,

Chun-Hua Cheng,

Chia-Ming Chang,

Yow-Tyng NiehAuthors Info & Claims

DAC '07: Proceedings of the 44th annual Design Automation Conference

Pages 970 - 975

https://doi.org/10.1145/1278480.1278720

Published: 04 June 2007 Publication History

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Abstract

The combination of clock skew scheduling and delay insertion may lead to further clock period reduction. Although some previous works can minimize the clock period, they only heuristically reduce the required inserted delay. However, since the delay insertion is an ECO (engineering change order) process, minimizing the required inserted delay is very important for the design closure, In this paper, we present a linear program to formally formulate the simultaneous application of clock skew scheduling and delay insertion. Our objective is not only to achieve the lower bound of the clock period, but also to achieve the lower bound of required inserted delay. Compared with previous works, our paper has the following two significant contributions: (1) our approach is the first work that guarantees solving this problem optimally; and (2) our paper is the first proof of showing that the time complexity of this problem is polynomial.

References

[1]

J. P. Fishburn, "Clock Skew Optimization", IEEE Trans. on Computers, vol. 39, No. 7, pp. 945--951, 1990.

Digital Library

Google Scholar

[2]

R. B. Deokar and S. S. Sapatnekar, "A Graph-Theoretic Approach to Clock Skew Optimization", Proc. of IEEE International Symposium on Circuits and Systems, vol. 1, pp.407--410, 1994.

Crossref

Google Scholar

[3]

C. Albrecht, B. Korte, J. Schietke, and J. Vygen, "Cycle Time and Slack Optimization for VLSI Chips", Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 232--238, 1999.

Digital Library

Google Scholar

[4]

N. V. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Minimum Padding to Satisfy Short Path Constraints", Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 156--161, 1993.

Digital Library

Google Scholar

[5]

S. H. Huang and Y. T. Nieh, "Clock Period Minimization of Non-Zero Clock Skew Circuits", Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 809--812, 2003.

Digital Library

Google Scholar

[6]

S. H. Huang and Y. T. Nieh, "Synthesis of Nonzero Clock Skew Circuits", IEEE Trans, on Computer Aided Design of Integrated Circuits and Systems, vol. 25, no.6, pp. 961--976, 2006.

Digital Library

Google Scholar

[7]

S. H. Huang, Y. T. Nieh, and F. P. Lu, "Race-Condition-Aware Clock Skew Scheduling", Proc. of IEEE/ACM Design Automation Conference, pp. 475--478, 2005.

Digital Library

Google Scholar

[8]

B. Taskin and I. S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 25, no.4, pp. 651--663, 2006.

Digital Library

Google Scholar

[9]

N. Karmarkar, "A New Polynomial-Time Algorithm for Linear Programming", Combinatorica, vol. 4, no. 4, pp. 373--395, 1984.

Digital Library

Google Scholar

[10]

M. C. Papaefthymiou, "Understanding Retiming through Maximum Average-Delay Cycles", Mathematical Systems Theory, vol. 27, pp. 65--84, 1994.

Digital Library

Google Scholar

Cited By

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Chiu WJiang ILu CChang Y(2017)Power and Area Efficient Hold Time Fixing by Free Metal Segment AllocationProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062303(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062303
Liu WSalman ESitik CTaskin BJones ALi HCoskun AMargala M(2015)Clock Skew Scheduling in the Presence of Heavily Gated Clock NetworksProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742092(283-288)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742092
Tyagi SDwivedi APal BIslam A(2015)Revisiting performance of various delay elements to realize a trigger pulse generator2015 International Conference on Smart Sensors and Systems (IC-SSS)10.1109/SMARTSENS.2015.7873605(1-6)Online publication date: Dec-2015
https://doi.org/10.1109/SMARTSENS.2015.7873605
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Index Terms

Clock period minimization with minimum delay insertion
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization

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Published In

DAC '07: Proceedings of the 44th annual Design Automation Conference

June 2007

1016 pages

ISBN:9781595936271

DOI:10.1145/1278480

General Chair:
Steven P. Levitan
Univ. of Pittsburgh, Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 04 June 2007

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DAC07: The 44th Annual Design Automation Conference 2007

June 4 - 8, 2007

California, San Diego

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DAC '07 Paper Acceptance Rate 152 of 659 submissions, 23%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Chiu WJiang ILu CChang Y(2017)Power and Area Efficient Hold Time Fixing by Free Metal Segment AllocationProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062303(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062303
Liu WSalman ESitik CTaskin BJones ALi HCoskun AMargala M(2015)Clock Skew Scheduling in the Presence of Heavily Gated Clock NetworksProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742092(283-288)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742092
Tyagi SDwivedi APal BIslam A(2015)Revisiting performance of various delay elements to realize a trigger pulse generator2015 International Conference on Smart Sensors and Systems (IC-SSS)10.1109/SMARTSENS.2015.7873605(1-6)Online publication date: Dec-2015
https://doi.org/10.1109/SMARTSENS.2015.7873605
Zhou XLuk WZhou HYang FYan CZeng X(2015)Multi-parameter clock skew schedulingIntegration, the VLSI Journal10.1016/j.vlsi.2014.07.00548:C(129-137)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.07.005
Yeh HHuang SNieh YFettweis GNebel W(2014)Leakage-power-aware clock period minimizationProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616991(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616991
Wu PWong MNedelchev IBhardwaj SParkhe V(2014)On Timing ClosureProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593171(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593171
Yang YJiang IHo S(2014)PushPullIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.230468133:4(558-570)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TCAD.2014.2304681
Tu WChou CHuang SChang SNieh YChou CHenkel J(2013)Low-power timing closure methodology for ultra-low voltage designsProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561964(697-704)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561964
Tu WHuang SCheng CMacii E(2013)Co-synthesis of data paths and clock control paths for minimum-period clock gatingProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485720(1831-1836)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485720
Yang YJiang IHo SKoh CSze C(2013)PushPullProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451928(50-57)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451928
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References

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Recommendations

Race-condition-aware clock skew scheduling

Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion

Delay insertion method in clock skew scheduling

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