Article

An efficient mechanism for performance optimization of variable-latency designs

Authors:

Yu-Shih Su,

Da-Chung Wang,

Shih-Chieh Chang,

Malgorzata Marek-SadowskaAuthors Info & Claims

DAC '07: Proceedings of the 44th annual Design Automation Conference

Pages 976 - 981

https://doi.org/10.1145/1278480.1278721

Published: 04 June 2007 Publication History

Get Access

Abstract

In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case conditions could lead to inefficient resource use. It is possible to improve the throughput of such circuits by introducing variable latency. One of the existing realizations of variable-latency design style is based on Telescopic Units. The design of the hold logic in telescopic units influences the circuit's throughput. In this paper, we show that the traditionally-designed hold logic in telescopic units may be inaccurate. We make use of the short path activation conditions to obtain more accurate hold logic than that commonly applied in the telescopic units. On average, our approach achieves a performance gain of 25.79% compared to 14.04%, which was reported in the previous works.

References

[1]

T. Austin, V. Bertacco, D. Blaauw, and T. Mudge, "Opportunities and Challenges for Better than Worst-Case Design," In Proceedings of the ASP-DAC 2005. Asia and South Pacific, vol. 1, pp. 1/2--1/7, 18--21 Jan. 2005.

Digital Library

Google Scholar

[2]

L. Benini, E. Macii, M. Poncino and G. De Micheli, "Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs," IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 3, pp. 220--232, Mar. 1998.

Digital Library

Google Scholar

[3]

L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, and M. Poncino, "Automatic Synthesis of large telescopic units based on near-minimum timed supersetting," IEEE Transaction on Computers, vol. 48, no. 8, pp. 769--779, Aug. 1999

Digital Library

Google Scholar

[4]

L. Benini, E. Macii and M. Poncino, "Efficient Controller Design for Telescopic Units," In Proceedings of IEEE International Conference Innovative Systems in Silicon, pp.290--299, Oct. 1997.

Google Scholar

[5]

Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, and Trevor Mudge, "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," 36rd Annual International Symposium on Microarchitecture(MICRO-36), pp. 7--18, December 2003.

Digital Library

Google Scholar

[6]

Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya, "Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units," In Proceedings of the ASP-DAC 2003. Asia and South Pacific, pp. 816--819, 21--24 Jan. 2003

Digital Library

Google Scholar

[7]

Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang, "Efficient Boolean Characteristic Function for Fast Timed ATPG," ICCAD'06, November 5--9, 2006.

Digital Library

Google Scholar

[8]

P. C. McGeer and R. K. Brayton, Integration Functional and Temporal Domains in Logic Synthesis. Boston, Mass.:Kluwer Academic 1991.

Digital Library

Google Scholar

[9]

S. F. Oberman and M. J. Flynn, "Design Issues in Division and Other Floating-Point Operations," IEEE Trans. Computers, vol. 46, no. 2, pp. 154--161, Feb. 1997.

Digital Library

Google Scholar

Cited By

View all

Huang NCheng CWu K(2022)Timing Variability-Aware Analysis and Optimization for Variable-Latency DesignsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.310982430:1(81-94)Online publication date: Jan-2022
https://doi.org/10.1109/TVLSI.2021.3109824
Tsai CCheng CHuang NWu K(2017)Analysis and optimization of variable-latency designs in the presence of timing variabilityProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130665(1219-1224)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130665
Du KVarman PMohanram KRosenstiel WMacii E(2012)High performance reliable variable latency carry select additionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493017(1257-1262)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493017
Show More Cited By

Index Terms

An efficient mechanism for performance optimization of variable-latency designs
1. Hardware
  1. Integrated circuits
    1. Logic circuits

Recommendations

A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry

Multiple-valued quantum logic circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum logic circuits. Adder/subtractor is the major component of the ALU of a computer and is also ...
Efficient retiming of large circuits

Retiming, introduced by Leiserson and Saxe, is a powerful transformation of circuits that preserves functionality and improves performance. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock ...
Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI

The superconducting rapid single flux quantum (RSFQ) logic circuit has the characteristics of high speed and low power consumption, making it an attractive candidate for future supercomputers. However, computer-aided design (CAD) tools for CMOS cannot ...

Comments

Information & Contributors

Information

Published In

DAC '07: Proceedings of the 44th annual Design Automation Conference

June 2007

1016 pages

ISBN:9781595936271

DOI:10.1145/1278480

General Chair:
Steven P. Levitan
Univ. of Pittsburgh, Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 04 June 2007

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC07

Sponsor:

SIGDA

DAC07: The 44th Annual Design Automation Conference 2007

June 4 - 8, 2007

California, San Diego

Acceptance Rates

DAC '07 Paper Acceptance Rate 152 of 659 submissions, 23%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
176
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 08 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Huang NCheng CWu K(2022)Timing Variability-Aware Analysis and Optimization for Variable-Latency DesignsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.310982430:1(81-94)Online publication date: Jan-2022
https://doi.org/10.1109/TVLSI.2021.3109824
Tsai CCheng CHuang NWu K(2017)Analysis and optimization of variable-latency designs in the presence of timing variabilityProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130665(1219-1224)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130665
Du KVarman PMohanram KRosenstiel WMacii E(2012)High performance reliable variable latency carry select additionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493017(1257-1262)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2493017
Galceran-Oms MGotmanov ACortadella JKishinevsky M(2011)Microarchitectural Transformations Using ElasticityACM Journal on Emerging Technologies in Computing Systems10.1145/2043643.20436487:4(1-24)Online publication date: 1-Dec-2011
https://dl.acm.org/doi/10.1145/2043643.2043648
Lin THsiao PLin CKuo SLin CKuo YLiu CChu YBahar RLombardi FAtienza DBrunvand E(2010)Collaborative voltage scaling with online STA and variable-latency datapathProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785560(347-352)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785560
(2010)Elastic systemsProceedings of the Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2010.5558639(149-158)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/MEMCOD.2010.5558639
Banñeres DCortadella JKishinevsky MBenini LDe Micheli GAl-Hashimi BMueller W(2009)Variable-latency design by function speculationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1875026(1704-1709)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1875026
Choudhury MMohanram KBenini LDe Micheli GAl-Hashimi BMueller W(2009)Masking timing errors on speed-paths in logic circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874642(87-92)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874642
Wan LChen DRoychowdhury J(2009)DynaTuneProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687430(172-179)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687430
Choudhury MMohanram K(2009)Timing-driven optimization using lookahead logic circuitsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630015(390-395)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630015
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry

Efficient retiming of large circuits

Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations