Article

Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors

Authors:

Keith A. Bowman,

Alaa R. Alameldeen,

Srikanth T. Srinivasan,

Chris B. WilkersonAuthors Info & Claims

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

Pages 50 - 55

https://doi.org/10.1145/1283780.1283792

Published: 27 August 2007 Publication History

Abstract

A statistical performance simulator is developed to explore the impact of die-to-die (D2D) and within-die (WID) parameter variations on the distributions of maximum clock frequency (FMAX) and throughput for multi-core processors in a future 22nm technology.allThe simulator integrates a compact analytical throughput model, which captures the key dependencies of multi-core processors, into a statistical simulation framework that models the effects of D2D and WID parameter variations on critical path delays across a die. The salient contributions from this paper are: (1) Product-level variation analysis for multi-core processors must focus on throughput, rather than just FMAX, and (2) Multi-core processors are inherently more variation tolerant than single-core processors due to the larger impact of memory latency and bandwidth on overall throughput. To elucidate these two points, multi-core and single-core processors have a similar chip-level FMAX distribution (mean degradation of 9% and standard deviation of 5%) for multi-threaded applications. In contrast to single-core processors, memory latency and bandwidth constraints significantly limit the throughput dependency on FMAX in multi-core processors, thus reducing the throughput mean degradation and standard deviation by 50%. Since single-threaded applications running on a multi-core processor can execute on the fastest core, mean FMAX and throughput gains of 4% are achieved from the nominal design target.

References

[1]

P. Gelsinger, "Microprocessors for the New Millennium: Challenges, Opportunities, and New Frontiers," in IEEE ISSCC, Feb. 2001, pp. 22--25.

[2]

M. Horowitz and W. Dally, "How Scaling Will Change Processor Architecture," in IEEE ISSCC, Feb. 2004, pp. 132--133.

[3]

M. Horowitz, et al., "Scaling, Power, and the Future of CMOS," in IEEE IEDM, Dec. 2005, pp. 11--17.

[4]

K. Bowman, S. Duvall, and J. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," IEEE JSSC, pp. 183--190, Feb. 2002.

[5]

International Technology Roadmap for Semiconductors (ITRS), Semiconductor Industry Association, www.itrs.net, 2006.

[6]

S. Borkar, et al., "Parameter Variations and Impact on Circuits and Microarchitecture," in 40th DAC Proc., June 2003, pp. 338--342.

Digital Library

[7]

S. Duvall, "Statistical Circuit Modeling and Optimization," in 5th Intl. Workshop Statistical Metrology, June 2000, pp. 56--63.

[8]

H. Masuda, et al., "Challenge: Variability Characterization and Modeling for 65- to 90-nm Processes," in IEEE CICC, Sept. 2005, pp. 593--600.

[9]

S. Samaan, "The Impact of Device Parameter Variations on the Frequency and Performance of Microprocessor Circuits," in IEEE ISSCC Microprocessor Circuit Design Forum, Feb. 2004.

[10]

J. Tschanz, et al., "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," IEEE JSSC, pp. 1396--1402, Nov. 2002.

[11]

Y. Abulafia and A. Kornfeld, "Estimation of FMAX and ISB in Microprocessors," IEEE Trans. VLSI Syst., pp. 1205--1209, Oct. 2005.

Digital Library

[12]

HSPICE User's Manual, Meta-Software Inc., Mar. 1995.

[13]

P. Bai, et al., "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 mm2 SRAM Cell," in IEEE IEDM, Dec. 2004, pp. 657--660.

[14]

M. Eisele, et al., "The Impact of Intra-Die Device Parameter Variations on Path Delays and on the Design for Yield of Low Voltage Digital Circuits," IEEE Trans. VLSI Syst., pp. 360--368, Dec. 1997.

Digital Library

[15]

J. Schutz and C. Webb, "A Scalable X86 CPU Design for 90nm Process," in IEEE ISSCC, Feb. 2004, pp. 62--63.

[16]

P. Dubey, "A Platform 2015 Model: Recognition, Mining and Synthesis Moves Computers to the Era of Tera," Intel Corp., Feb. 2005, download.intel.com/technology/computing/archinnov/platform2015/download/RMS.pdf.

[17]

A. Alameldeen, Using Compression to Improve Chip Multiprocessor Performance, PhD Thesis, University of Wisconsin, 2006.

Digital Library

[18]

T. Karkhanis and J. Smith, "A First-Order Superscalar Processor Model," in Proc. of 31st Annual Intl. Symp. Comp. Arch., June 2004, pp. 338--349.

Digital Library

[19]

J. Emer, et al., "ASIM: A Performance Model Framework," IEEE Computer, pp. 68--76, Feb. 2002.

Digital Library

[20]

Microprocessor Quick Reference Guide, Intel Corp., www.intel.com/pressroom/kits/quickrefyr.htm.

Digital Library

[21]

SPEC Benchmarks, Systems Performance Evaluation Corp., www.spec.org.

[22]

J. Doweck, "Inside the CORETM Microarchitecture," in HotChips, Aug. 2006.

[23]

S. Rusu, et al., "A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache," in IEEE ISSCC, Feb. 2006, pp. 102--103.

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Index Terms

Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors
1. Hardware
  1. Robustness

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cover image ACM Conferences

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

August 2007

432 pages

ISBN:9781595937094

DOI:10.1145/1283780

General Chairs:
Diana Marculescu
Carnegie Mellon University
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Ali Keshavarzi
Intel Corporation
,
Vijaykrishnan Narayanan
Penn State University

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 27 August 2007

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ISLPED07

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ISLPED07: International Symposium on Low Power Electronics and Design

August 27 - 29, 2007

OR, Portland, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cai EJuan DGarg SPark JMarculescu D(2016)Learning-Based Power/Performance Optimization for Many-Core Systems With Extended-Range Voltage/Frequency ScalingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.250433035:8(1318-1331)Online publication date: 1-Aug-2016
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Nittala RBarchi FUrgese GAcquaviva A(2016)Toolchain integration of runtime variability and aging awareness in multicore platforms2016 Forum on Specification and Design Languages (FDL)10.1109/FDL.2016.7880384(1-8)Online publication date: Sep-2016
https://doi.org/10.1109/FDL.2016.7880384
Srivastav MEhteshamuddin MStegner KNazhandali L(2015)Design of Ultra-Low Power Scalable-Throughput Many-Core DSP ApplicationsACM Transactions on Design Automation of Electronic Systems10.1145/272001820:3(1-21)Online publication date: 24-Jun-2015
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Gray IAcquaviva AAudsley N(2014)Designing Resource-Constrained Embedded Heterogeneous Systems to Cope with VariabilityHandbook of Research on Embedded Systems Design10.4018/978-1-4666-6194-3.ch004(75-101)Online publication date: 2014
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