Article

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs

Authors:

Yao-Wen ChangAuthors Info & Claims

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

Pages 92 - 97

https://doi.org/10.1145/1283780.1283801

Published: 27 August 2007 Publication History

Abstract

As technology continues to shrink, leakage power becomes animportant issue for modern FPGAs. In this paper, we address the leakage issue of partially dynamical reconfigurable FPGAs. We focus on eliminating leakage waste due to the delay between reconfiguration and task execution. We propose a post-placement leakage-aware scheduling algorithm that refines a placement generated by a performance-driven scheduler such that leakage waste is minimized and performance is not sacrificed. Experimental results on real and synthetic designs demonstrate the effectiveness and efficiency of our algorithm on leakage optimization.

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Cited By

Tianyang LFan ZWei GMingqian SLi C(2021)A Survey: FPGA‐Based Dynamic Scheduling of Hardware TasksChinese Journal of Electronics10.1049/cje.2021.07.02130:6(991-1007)Online publication date: Nov-2021
https://doi.org/10.1049/cje.2021.07.021
Jing CZhu YLi M(2018)Energy-efficient scheduling on multi-FPGA reconfigurable systemsMicroprocessors & Microsystems10.1016/j.micpro.2013.05.00137:6-7(590-600)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.micpro.2013.05.001
Ahari AEbrahimi MTahoori M(2015)Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7293947(1-6)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7293947
Show More Cited By

Index Terms

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
1. Hardware
  1. Hardware validation

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Active leakage power optimization for FPGAs

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Published In

cover image ACM Conferences

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

August 2007

432 pages

ISBN:9781595937094

DOI:10.1145/1283780

General Chairs:
Diana Marculescu
Carnegie Mellon University
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Ali Keshavarzi
Intel Corporation
,
Vijaykrishnan Narayanan
Penn State University

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 27 August 2007

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ISLPED07

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ISLPED07: International Symposium on Low Power Electronics and Design

August 27 - 29, 2007

OR, Portland, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Tianyang LFan ZWei GMingqian SLi C(2021)A Survey: FPGA‐Based Dynamic Scheduling of Hardware TasksChinese Journal of Electronics10.1049/cje.2021.07.02130:6(991-1007)Online publication date: Nov-2021
https://doi.org/10.1049/cje.2021.07.021
Jing CZhu YLi M(2018)Energy-efficient scheduling on multi-FPGA reconfigurable systemsMicroprocessors & Microsystems10.1016/j.micpro.2013.05.00137:6-7(590-600)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.micpro.2013.05.001
Ahari AEbrahimi MTahoori M(2015)Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7293947(1-6)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7293947
Jing C(2015)Ant-Colony Optimization Based Algorithm for Energy-Efficient Scheduling on Dynamically Reconfigurable SystemsProceedings of the 2015 Ninth International Conference on Frontier of Computer Science and Technology10.1109/FCST.2015.10(127-134)Online publication date: 26-Aug-2015
https://dl.acm.org/doi/10.1109/FCST.2015.10
Hsieh JChang YLee W(2011)An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950944(661-667)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950944
Hsieh JChang YLee W(2011)An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)10.1109/ASPDAC.2011.5722270(661-667)Online publication date: Jan-2011
https://doi.org/10.1109/ASPDAC.2011.5722270

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