Article

Power-efficient LDPC code decoder architecture

Authors:

Kazunori Shimizu,

Nozomu Togawa,

Takeshi Ikenaga,

Satoshi GotoAuthors Info & Claims

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

Pages 359 - 362

https://doi.org/10.1145/1283780.1283858

Published: 27 August 2007 Publication History

Get Access

Abstract

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.

References

[1]

D. J. C. MacKay, "Good error-correctiong codes based on very sparse matrices," IEEE Trans. on Information Theory, Vol.47, pp. 498--519, 2001.

Digital Library

Google Scholar

[2]

M. Mansour and N. Shanbhag, "Low Power VLSI Decoder Architectures for LDPC Codes," Proceedings of the International Symposium on Low Power Electronics and Design, pp. 284--289, 2002.

Digital Library

Google Scholar

[3]

Yanni Chen and Keshab K. Parhi, "Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check Codes," IEEE Trans. on Circuits and Systems I, pp. 1106--1113, vol. 51, no. 6, 2004.

Crossref

Google Scholar

[4]

R. G. Gallager, Low-Density Parity-Check Codes, MIP Press, Cambridge, MA, 1963.

Google Scholar

[5]

A. Sridharan, D. J. Costello Jr, D. Sridhara, T. Fuja, and R. M. Tanner, "A construction for low-density parity check convolutional codes based on quasi-cyclic block codes," Proc. IEEE ISIT, p. 481, 2002.

Google Scholar

[6]

J. Chen and M. P. C. Fossorier, "Near optimum universal belief propagation based decoding of low-density parity-check codes," IEEE Trans. Commun., vol.50, pp. 406--414, Mar. 2002.

Crossref

Google Scholar

Cited By

View all

Kim EShanbhag N(2012)Energy-Efficient LDPC Decoders Based on Error-ResiliencyProceedings of the 2012 IEEE Workshop on Signal Processing Systems10.1109/SiPS.2012.60(149-154)Online publication date: 17-Oct-2012
https://dl.acm.org/doi/10.1109/SiPS.2012.60
Xiang BBao DHuang SZeng X(2011)An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $\mu$m CMOSIEEE Journal of Solid-State Circuits10.1109/JSSC.2011.212503046:6(1416-1432)Online publication date: Jun-2011
https://doi.org/10.1109/JSSC.2011.2125030
Yeong-Luh Ueng Chung-Jay Yang Zong-Cheng Wu Chen-Eng Wu Yu-Lun Wang (2008)VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX2008 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2008.4541469(520-523)Online publication date: May-2008
https://doi.org/10.1109/ISCAS.2008.4541469

Index Terms

Power-efficient LDPC code decoder architecture

Recommendations

A Flexible LDPC/Turbo Decoder Architecture

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be ...
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-...
An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications

In this paper, an area efficient and high throughput multi-rate quasi-cyclic low-density parity-check (QC-LDPC) decoder for IEEE 802.11n applications is proposed. An overlapped message passing scheme and the non-uniform quantization scheme are ...

Comments

Information & Contributors

Information

Published In

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

August 2007

432 pages

ISBN:9781595937094

DOI:10.1145/1283780

General Chairs:
Diana Marculescu
Carnegie Mellon University
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Ali Keshavarzi
Intel Corporation
,
Vijaykrishnan Narayanan
Penn State University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 August 2007

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ISLPED07

Sponsor:

ISLPED07: International Symposium on Low Power Electronics and Design

August 27 - 29, 2007

OR, Portland, USA

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
226
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 02 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Kim EShanbhag N(2012)Energy-Efficient LDPC Decoders Based on Error-ResiliencyProceedings of the 2012 IEEE Workshop on Signal Processing Systems10.1109/SiPS.2012.60(149-154)Online publication date: 17-Oct-2012
https://dl.acm.org/doi/10.1109/SiPS.2012.60
Xiang BBao DHuang SZeng X(2011)An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $\mu$m CMOSIEEE Journal of Solid-State Circuits10.1109/JSSC.2011.212503046:6(1416-1432)Online publication date: Jun-2011
https://doi.org/10.1109/JSSC.2011.2125030
Yeong-Luh Ueng Chung-Jay Yang Zong-Cheng Wu Chen-Eng Wu Yu-Lun Wang (2008)VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX2008 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2008.4541469(520-523)Online publication date: May-2008
https://doi.org/10.1109/ISCAS.2008.4541469

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

A Flexible LDPC/Turbo Decoder Architecture

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations