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A low-power CSCD asynchronous viterbi decoder for wireless applications

Published: 27 August 2007 Publication History

Abstract

This paper presents a 64-state, ½-rate asynchronous Viterbi decoder suitable for wireless and mobile applications. The decoder uses a novel dynamic Current Sensing Completion Detection (CSCD) technique and achieves significant power reduction while maintaining speed. The decoder, implemented in a 90 nm CMOS technology, occupies an area of 0.81 mm2 and operates at 378 Mb/s while consuming 45 mW: a 43% power delay product improvement when compared to its synchronous counterpart.

References

[1]
B. P. Lathi, "Modern Digital and Analog Communication Systems," Oxford University Press, New York, 1998.
[2]
M. Kawokgy and C. A. T. Salama, "Low-Power Asynchronous Viterbi Decoder for Wireless Applications," International Symposium on Low Power Electronics and Design, pp. 286--289, 2004.
[3]
J. Sparso and S. Furber (EDs.), "Principles of Asynchronous Circuit Design," Kluwer Academic Publishers, Boston, 2001.
[4]
H. Lampinen and O. Vainio, "Dynamically Biased Current Sensor for Current-Sensing Completion Detection," IEEE International Symposium on Circuits and Systems, Proceedings, pp. 394--397, 2001.

Cited By

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  • (2017)A low power asynchronous Viterbi decoder using minimum transition hybrid register exchange method2017 International Conference On Smart Technologies For Smart Nation (SmartTechCon)10.1109/SmartTechCon.2017.8358357(137-142)Online publication date: Aug-2017
  • (2013)Completion detection in dual-rail asynchronous systems by current-sensingMicroelectronics Journal10.1016/j.mejo.2013.03.01444:6(538-544)Online publication date: Jun-2013
  • (2012)Viterbi Accelerator for Embedded Processor DatapathsProceedings of the 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2012.24(133-140)Online publication date: 9-Jul-2012

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cover image ACM Conferences
ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design
August 2007
432 pages
ISBN:9781595937094
DOI:10.1145/1283780
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 August 2007

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Author Tags

  1. asynchronous
  2. current sensing completion detection
  3. digital signal processing
  4. handshaking
  5. low-power
  6. synchronous
  7. viterbi
  8. wireless

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all
  • (2017)A low power asynchronous Viterbi decoder using minimum transition hybrid register exchange method2017 International Conference On Smart Technologies For Smart Nation (SmartTechCon)10.1109/SmartTechCon.2017.8358357(137-142)Online publication date: Aug-2017
  • (2013)Completion detection in dual-rail asynchronous systems by current-sensingMicroelectronics Journal10.1016/j.mejo.2013.03.01444:6(538-544)Online publication date: Jun-2013
  • (2012)Viterbi Accelerator for Embedded Processor DatapathsProceedings of the 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2012.24(133-140)Online publication date: 9-Jul-2012

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