Cited By
View all- Tadse SHaridas S(2017)A low power asynchronous Viterbi decoder using minimum transition hybrid register exchange method2017 International Conference On Smart Technologies For Smart Nation (SmartTechCon)10.1109/SmartTechCon.2017.8358357(137-142)Online publication date: Aug-2017
- Nagy LStopjakova VZalusky R(2013)Completion detection in dual-rail asynchronous systems by current-sensingMicroelectronics Journal10.1016/j.mejo.2013.03.01444:6(538-544)Online publication date: Jun-2013
- Azhar MSjalander MAli HVijayashekar AHoang TAnsari KLarsson-Edefors P(2012)Viterbi Accelerator for Embedded Processor DatapathsProceedings of the 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2012.24(133-140)Online publication date: 9-Jul-2012