Article

Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS

Authors:

Antonio J. Ginés,

Eduardo J. Peralías,

Adoración RuedaAuthors Info & Claims

SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems design

Pages 21 - 26

https://doi.org/10.1145/1284480.1284494

Published: 03 September 2007 Publication History

Abstract

A novel swapping technique for calibration of the stage non-linear errors in Pipeline ADCs is proposed in this paper. The algorithm obtains an estimation of the mismatching between sampling capacitors in practical SC implementations of the multiplying-DAC without the necessity of interrupting the converter operation, and therefore, suitable for both foreground and background calibration applications. This work overcomes the practical limitations of previous adaptive approaches based on the capacitor swapping introducing a novel modulation scheme which minimizes the impact on the analogue part and employs a simple calibration logic.

References

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B. Song, F. Tompsett and K. Lakshmikumar, "A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter," IEEE J. of Solid-State Circuits, vol. 23, Dec. 1988, pp. 1324--1333.

[2]

Y. Chiu, "Inherently linear capacitor error-averaging techniques for pipelined A/D conversion," IEEE Trans. Circuits and Systems II, vol. 47, Mar. 2000, pp. 229--232.

[3]

P. Rombouts and L. Weyten, "A digital error-averaging technique for pipelined A/D conversion," IEEE Trans. Circuits and Systems II, vol. 45, Sept. 1998, pp. 1321--1323.

[4]

A.J. Ginés, E.J. Peralías and A. Rueda. "Full calibration digital techniques for pipeline ADCs," IEEE Int. Sym. Circuits and Systems, ISCAS, vol. 3, May 2005, pp. 1976--1979.

[5]

H.C. Liu, Z.M. Lee and J.T. Wu. "A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration," IEEE J. of Solid-State Circuits, vol.40, no.5, May 2005, pp. 1047--1056.

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E. Siragusa and I. Galton, "A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC," IEEE J. of Solid-State Circuits, vol. 39, Dec. 2004, pp.2126--2138.

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E. J. Siragusa and I. Galton, "Gain error correction technique for pipelined analogue-to-digital converters," IEE Electronics Letters, vol. 36, Mar. 2000, pp.617--618.

[8]

J. Li and U. K. Moon, "Background calibration techniques for multistage pipelined ADC's with digital redundancy," IEEE Trans. Circuits and Systems II, Analog and Digital Signal Processing, vol.50, no.9, Sep.2003, pp.531--538.

[9]

A.J. Ginés, E.J. Peralías and A. Rueda, "Gain Error Correction in Pipeline ADCswith Digital Redundancy," Proc. of IEEJ International Analog VLSI Workshop, AVLSIWS, Oct. 2004, pp.155--160.

[10]

B. Murmann and B. E. Boser, ."A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE J. of Solid-State Circuits, vol. 38, Dec. 2003, pp. 2040--2050.

[11]

A. J. Ginés, E. J. Peralías and A. Rueda. "Noisy signal based background technique for gain error correction in pipeline ADCs," Proc. of IEE Computers and Digital Techniques, CDT, vol.152, no.1, 14 Jan. 2005, pp.53--63.

[12]

K. El-Sankary and M. Sawan, "A Digital Blind Background Capacitor Mismatch Calibration for Pipelined ADC," IEEE Trans. Circuits and Sys. II, vol. 51, Oct. 2004, pp. 507--510.

[13]

I. Galton. "Digital cancellation of D/A converter noise in pipelined A/D converters," IEEE Trans. Circuits and Systems II, vol.47, no.3, Mar 2000, pp.185--196.

[14]

M. Taherzadeh-Sani and A. Hamoui, "Digital Background Calibration of Capacitor Mismatch Errors in Pipelined ADCs," IEEE Trans. Circuits and Sys.II; future publication.

[15]

P. Yu and H. Lee, "A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC," IEEE J. of Solid-State Circuits, vol. 31, Dec. 1996, pp. 1854--1861.

Cited By

Gines APeralias ERueda A(2009)A survey on digital background calibration of ADCs2009 European Conference on Circuit Theory and Design10.1109/ECCTD.2009.5274976(101-104)Online publication date: Aug-2009
https://doi.org/10.1109/ECCTD.2009.5274976
Ginés APeralías ERueda A(2008)New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCsAnalog Integrated Circuits and Signal Processing10.1007/s10470-008-9195-457:1-2(57-68)Online publication date: 1-Nov-2008
https://dl.acm.org/doi/10.1007/s10470-008-9195-4

Index Terms

Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS
1. Hardware
  1. Integrated circuits
    1. Interconnect
      1. Input / output circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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cover image ACM Conferences

SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems design

September 2007

382 pages

ISBN:9781595938169

DOI:10.1145/1284480

General Chair:
Antonio Petraglia
UFRJ, Brazil
,
Program Chairs:
Volnei A. Pedroni
UTFPR, Brazil
,
Gert Cauwenberghs
UCSD

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 03 September 2007

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SBCCI07

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SBCCI07: 20th Symposium on Integrated Circuits and System Design

September 3 - 6, 2007

Copacabana, Rio de Janeiro

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Gines APeralias ERueda A(2009)A survey on digital background calibration of ADCs2009 European Conference on Circuit Theory and Design10.1109/ECCTD.2009.5274976(101-104)Online publication date: Aug-2009
https://doi.org/10.1109/ECCTD.2009.5274976
Ginés APeralías ERueda A(2008)New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCsAnalog Integrated Circuits and Signal Processing10.1007/s10470-008-9195-457:1-2(57-68)Online publication date: 1-Nov-2008
https://dl.acm.org/doi/10.1007/s10470-008-9195-4

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