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Cache coherency communication cost in a NoC-based MPSoC platform

Published: 03 September 2007 Publication History

Abstract

Cache coherency and cache consistency in NoC-based heterogeneous platforms are still open problems. Current works addressing platform design avoid this issue either by proposing cacheless implementations or using snoopy protocols over buses. This paper addresses the cache coherence problem in a NoC-based MPSoC platform, focusing the communication considering both the load overhead produced by the coherency mechanism and read/write response times. Simulations of applications written in C and compiled with GCC are presented. Simulations results indicate that the load is constant with the cache size for a given line size.

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Cited By

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  • (2018)Hierarchical multicore thread mapping via estimation of remote communicationThe Journal of Supercomputing10.1007/s11227-017-2176-674:3(1321-1340)Online publication date: 1-Mar-2018
  • (2018)Managing Cache Memory Resources in Adaptive Many-Core SystemsSystem Level Design from HW/SW to Memory for Embedded Systems10.1007/978-3-319-90023-0_14(172-182)Online publication date: 17-Apr-2018
  • (2016)Hierarchical Cluster Based NoC Design Using Wireless Interconnects for Coherence SupportProceedings of the 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2016.54(63-68)Online publication date: 4-Jan-2016
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cover image ACM Conferences
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems design
September 2007
382 pages
ISBN:9781595938169
DOI:10.1145/1284480
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 03 September 2007

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Author Tags

  1. MPSoC
  2. NoC
  3. cache coherence
  4. directory

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SBCCI07
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SBCCI07: 20th Symposium on Integrated Circuits and System Design
September 3 - 6, 2007
Copacabana, Rio de Janeiro

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

View all
  • (2018)Hierarchical multicore thread mapping via estimation of remote communicationThe Journal of Supercomputing10.1007/s11227-017-2176-674:3(1321-1340)Online publication date: 1-Mar-2018
  • (2018)Managing Cache Memory Resources in Adaptive Many-Core SystemsSystem Level Design from HW/SW to Memory for Embedded Systems10.1007/978-3-319-90023-0_14(172-182)Online publication date: 17-Apr-2018
  • (2016)Hierarchical Cluster Based NoC Design Using Wireless Interconnects for Coherence SupportProceedings of the 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2016.54(63-68)Online publication date: 4-Jan-2016
  • (2016)Evaluation of the Memory Communication Traffic in a Hierarchical Cache Model for Massively-Manycore Processors2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)10.1109/PDP.2016.30(726-733)Online publication date: Feb-2016
  • (2015)IPNoSys IIProceedings of the 28th Symposium on Integrated Circuits and Systems Design10.1145/2800986.2801012(1-7)Online publication date: 31-Aug-2015
  • (2013)NoC-Based System IntegrationDesigning 2D and 3D Network-on-Chip Architectures10.1007/978-1-4614-4274-5_5(127-145)Online publication date: 9-Oct-2013
  • (2011)A minimalist cache coherent MPSoC designed for FPGAsInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2011.0404603:2/3(67-76)Online publication date: 1-May-2011
  • (2011)A Reconfigurable Computing System Based on a Cache-Coherent FabricProceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2011.4(80-85)Online publication date: 30-Nov-2011
  • (2010)Specification and verification of a MPI implementation for a MP-SoCProceedings of the 7th International colloquium conference on Theoretical aspects of computing10.5555/1881833.1881849(168-183)Online publication date: 1-Sep-2010
  • (2010)Evaluation of a hardware transactional memory model in an NoC-based embedded MPSoCProceedings of the 23rd symposium on Integrated circuits and system design10.1145/1854153.1854177(85-90)Online publication date: 6-Sep-2010
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