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A self-maintained memory module supporting DMM

Published: 30 September 2007 Publication History

Abstract

The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management (DMM); however, it is a challenging task to provide efficient reliable system without violating real time performance constraints. Hardware approach emerges as one of the candidate in improving the performance of DMM. This paper presents an efficient design for explicit dynamic memory management which exploits the high speed of a pure hardware implementation. Object allocation and deletion are strictly bounded in time. The whole heap space is divided into two semi-spaces, and a concurrent bidirectional memory compaction algorithm is proposed. So that memory compaction can be done while mutator process is running on the processor. A small built in object-based cache memory is available to avoid indirect object addressing inefficiencies. Experiments show that this hardware scheme can greatly improve the speed and predictability of DMM.

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Cited By

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  • (2009)A Parallel Memory System Model for Multi-core ProcessorProceedings of the 2009 IEEE International Conference on Networking, Architecture, and Storage10.1109/NAS.2009.48(219-222)Online publication date: 9-Jul-2009
  • (2009)Low Overhead Object Communication Scheme in CMP Implementation of Object-Oriented ProgrammingProceedings of the 2009 15th International Conference on Parallel and Distributed Systems10.1109/ICPADS.2009.35(925-930)Online publication date: 8-Dec-2009
  • (2009)Storage Architecture for an On-chip Multi-core ProcessorProceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools10.1109/DSD.2009.213(263-270)Online publication date: 27-Aug-2009
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cover image ACM Conferences
CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
September 2007
292 pages
ISBN:9781595938268
DOI:10.1145/1289881
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 September 2007

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Author Tags

  1. active memory module
  2. dynamic memory management
  3. object-based cache
  4. object-oriented programming

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ESWEEK07
ESWEEK07: Third Embedded Systems Week
September 30 - October 3, 2007
Salzburg, Austria

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

View all
  • (2009)A Parallel Memory System Model for Multi-core ProcessorProceedings of the 2009 IEEE International Conference on Networking, Architecture, and Storage10.1109/NAS.2009.48(219-222)Online publication date: 9-Jul-2009
  • (2009)Low Overhead Object Communication Scheme in CMP Implementation of Object-Oriented ProgrammingProceedings of the 2009 15th International Conference on Parallel and Distributed Systems10.1109/ICPADS.2009.35(925-930)Online publication date: 8-Dec-2009
  • (2009)Storage Architecture for an On-chip Multi-core ProcessorProceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools10.1109/DSD.2009.213(263-270)Online publication date: 27-Aug-2009
  • (2009)High Performance Memory Management for a Multi-core ArchitectureProceedings of the 2009 Ninth IEEE International Conference on Computer and Information Technology - Volume 0210.1109/CIT.2009.120(63-68)Online publication date: 11-Oct-2009

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