Article

Cache leakage control mechanism for hard real-time systems

Authors:

Jien-Jia ChenAuthors Info & Claims

CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems

Pages 248 - 256

https://doi.org/10.1145/1289881.1289924

Published: 30 September 2007 Publication History

Abstract

Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transistor budget, several leakage control policies have been proposed to reduce cache leakage. However, these policies introduce performance unpredictability thereby not suitable for hard real-time applications that require the timing constraint is met in all cases. In this paper, we propose the first approach to apply existing low leakage circuit techniques on hard real-time applications. The proposed timing-aware cache leakage control mechanism exploits task slack time to turn cache lines into the low-leakage state provided that the timing constraint is met. The experimental results show that the proposed cache leakage control policy achieves comparable leakage reduction to the leakage control policy that aggressively turn cache lines into low-leakage modes without considering the timing constraint.

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Cited By

Mittal SZhang ZCao Y(2013)CASHIERProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.160(43-48)Online publication date: 5-Jan-2013
https://dl.acm.org/doi/10.1109/VLSID.2013.160
Weixun Wang Mishra P(2012)System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.211681420:5(902-910)Online publication date: May-2012
https://doi.org/10.1109/TVLSI.2011.2116814
Wang WMishra PRanka SWang WMishra PRanka S(2012)System-Wide Energy Optimization with DVS and DCRDynamic Reconfiguration in Real-Time Systems10.1007/978-1-4614-0278-7_6(129-163)Online publication date: 30-Mar-2012
https://doi.org/10.1007/978-1-4614-0278-7_6
Show More Cited By

Index Terms

Cache leakage control mechanism for hard real-time systems
1. Hardware
  1. Hardware validation

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Published In

cover image ACM Conferences

CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems

September 2007

292 pages

ISBN:9781595938268

DOI:10.1145/1289881

General Chairs:
Taewhan Kim
Seoul National University, South Korea
,
Pascal Sainrat
IRIT - Université de Toulouse, France
,
Program Chairs:
Steven S. Lumetta
University of Illinois at Urbana-Champaign, USA
,
Nacho Navarro
Universitat Politecnica de Catalunya, Spain

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 September 2007

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ESWEEK07

Sponsor:

ESWEEK07: Third Embedded Systems Week

September 30 - October 3, 2007

Salzburg, Austria

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

Mittal SZhang ZCao Y(2013)CASHIERProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.160(43-48)Online publication date: 5-Jan-2013
https://dl.acm.org/doi/10.1109/VLSID.2013.160
Weixun Wang Mishra P(2012)System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.211681420:5(902-910)Online publication date: May-2012
https://doi.org/10.1109/TVLSI.2011.2116814
Wang WMishra PRanka SWang WMishra PRanka S(2012)System-Wide Energy Optimization with DVS and DCRDynamic Reconfiguration in Real-Time Systems10.1007/978-1-4614-0278-7_6(129-163)Online publication date: 30-Mar-2012
https://doi.org/10.1007/978-1-4614-0278-7_6
Wang WMishra P(2010)Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time SystemsProceedings of the 2010 23rd International Conference on VLSI Design10.1109/VLSI.Design.2010.22(357-362)Online publication date: 3-Jan-2010
https://dl.acm.org/doi/10.1109/VLSI.Design.2010.22

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