Article

Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip

Authors:

Emiliano Dolif,

Michele Lombardi,

Martino Ruggiero,

Michela Milano,

Luca BeniniAuthors Info & Claims

EMSOFT '07: Proceedings of the 7th ACM & IEEE international conference on Embedded software

Pages 47 - 56

https://doi.org/10.1145/1289927.1289940

Published: 30 September 2007 Publication History

Abstract

The increasing levels of system integration in Multi-Processor System-on-Chips (MPSoCs) emphasize the need for new design flows for efficient mapping of multi-task applications onto hardware platforms. Even though data-flow graphs are often used for pure data-streaming, many realistic applications can only be specified as conditional task graphs (CTG). The problem of allocating and scheduling conditional task graphs on processors in a distributed real-time system is NP-hard. The first contribution of this paper is a complete stochastic allocation and scheduling framework, where an MPSoC virtual platform is used to accurately derive input parameters, validate abstract models of system components and assess constraint satisfaction and objective function optimization. The optimizer implements an efficient and exact approach to allocation and scheduling based on problem decomposition. The original contributions of the approach appear both in the allocation and in the scheduling part of the optimizer. For the first, we propose an exact analytic formulation of the stochastic objective function based on the task graph analysis, while for the scheduling part we extend the timetable constraint for conditional activities. The second contribution of this paper is the introduction of a software library and API for the deployment of conditional task graph applications onto Multi-Processor System-on-Chips. With our library support, programmers can quickly develop multi-task applications which will run on a multi-core architecture and can easily apply the optimal solution found by our optimizer. The proposed programming support manages OS-level issues, such as task allocation and scheduling, as well as task-level issues, like inter-task communication and synchronization.

References

[1]

Rtems home page, http://www.rtems.com.

[2]

S. Ahmed and A. Shapiro. The sample average approximation method for stochastic programs with integer recourse. In: Optimization on line., 2002.

[3]

J. Axelsson. Architecture synthesis and partitioning of real-time systems: A comparison of three heuristic search strategies. In CODES '97.

Digital Library

[4]

A. Bender. Milp based task mapping for heterogeneous multiprocessor systems. In EURO-DAC '96/EURO-VHDL '96.

Digital Library

[5]

J. Benders. Partitioning procedures for solving mixed-variables programming problems. Computational Management Science, 2005.

[6]

L. Benini, D. Bertozzi, A. Guerri, and M. Milano. Allocation and scheduling for mpsocs via decomposition and no-good generation. In Proc. of the Int'l Conference in Principles and Practice of Constraint Programming.(2005).

[7]

B. Flachs. A streaming processor unit for the cell processor. In pp. 134--135, ISSCC 2005.

[8]

K. S. Chatha and R. Vemuri. Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Trans. Very Large Scale Integr. Syst.

Digital Library

[9]

P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, and P. Pop. Scheduling of conditional process graphs for the synthesis of embedded systems. In DATE '98.

Digital Library

[10]

P. Eles, Z. Peng, K. Kuchcinski, and A. Doboli. System level hardware/software partitioning based on simulated annealing and tabu search. In Journal on Design Automation for Embedded Systems, 1997.

[11]

A. Eremin and M. Wallace. Hybrid benders decomposition algorithms in constraint logic programming. In CP '01.

Digital Library

[12]

P. Faraboschi, J. Fisher, and C. Young. Instruction scheduling for instruction level parallel processors. Proceedings of the IEEE, pages 1638--1659, 2001.

[13]

P. Francesco, P. Antonio, and P. Marchal. Flexible hardware/software support for message passing on a distributed shared memory architecture. In DATE '05.

Digital Library

[14]

C. Gomes, B. Selman, K. McAloon, and C. Tretkoff. Randomization in backtrack search: Exploiting heavy-tailed profiles for solving hard scheduling problems. AIPS, pages 208--213, 1998.

[15]

J. N. Hooker. A hybrid method for planning and scheduling. In CP.

[16]

V. Jain and I. E. Grossmann. Algorithms for hybrid milp/cp models for a class of optimization problems. INFORMS J. on Computing.

Digital Library

[17]

S. Kodase, S. Wang, Z. Gu, and K. G. Shin. Improving scalability of task allocation and scheduling in large distributed real-time systems using shared buffers. In RTAS '03.

Digital Library

[18]

K. Kuchcinski. Constraints-driven scheduling and resource assignment. ACM Trans. Des. Autom. Electron. Syst.

Digital Library

[19]

K. Kuchcinski. Embedded system synthesis by timing constraint solving. In IEEE Transactions on CAD.

[20]

G. Laporte and F. Louveaux. The integer l-shaped method for stochastic integer programs with complete recourse. In: Operations Research Letters, 1993.

[21]

M. Lombardi and M. Milano. Stochastic allocation and scheduling for conditional task graphs in mpsocs. In Technical Report 77 LIA-003-06.

[22]

V. I. Norkin, G. C. Pflug, and A. Ruszczyński. A branch and bound method for stochastic global optimization. Math. Program., 1998.

Digital Library

[23]

P. Palazzari, L. Baldini, and M. Coli. Synthesis of pipelined systems for the contemporaneous execution of periodic and aperiodic tasks with hard real-time constraints. ipdps.

[24]

D. Pham and et al. The design and implementation of a first-generation cell processor.

[25]

S. Prakash and A. C. Parker. Sos: synthesis of application-specific heterogeneous multiprocessor systems.

[26]

M. Ruggiero, A. Guerri, D. Bertozzi, F. Poletti, and M. Milano. Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip. In DATE '06.

Digital Library

[27]

A. Semiconductor. Arm11 mpcore multiprocessor. In http://arm.convergencepromotions.com/catalog/753.htm.

[28]

R. Szymanek and K. Kuchcinski. A constructive algorithm for memory-aware task assignment and scheduling. In CODES '01.

Digital Library

[29]

S. A. Tarim, S. Manandhar, and T. Walsh. Stochastic constraint programming: A scenario-based approach. Constraints, 2006.

Digital Library

[30]

C. Technologies. The multi-core dsp advantage formultimedia. In Available at http://www.cradle.com/.

[31]

E. S. Thorsteinsson. Branch-and-check: A hybrid framework integrating mixed integer programming and constraint logic programming. In CP '01.

Digital Library

[32]

T. Walsh. Stochastic constraint programming. Proc. of ECAI, 2002.

[33]

D. Wu, B. Al-Hashimi, and P. Eles. Scheduling and mapping of conditional task graph for the synthesis of low power embedded systems. In Computers and Digital Techniques, IEE Proceedings. Volume 150 (5). (2003).

Digital Library

Cited By

Wang YShao ZChan HLiu DGuan Y(2014)Memory-Aware Task Scheduling with Communication Overhead Minimization for Streaming Applications on Bus-Based Multiprocessor System-on-ChipsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2013.17225:7(1797-1807)Online publication date: 1-Jul-2014
https://dl.acm.org/doi/10.1109/TPDS.2013.172
Wang YLiu DQin ZShao Z(2013)Optimally Removing Intercore Communication Overhead for Streaming Applications on MPSoCsIEEE Transactions on Computers10.1109/TC.2011.23662:2(336-350)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TC.2011.236
Hsiu PHsieh CLee DKuo T(2012)Multilayer Bus Optimization for Real-Time Embedded SystemsIEEE Transactions on Computers10.1109/TC.2011.20061:11(1638-1650)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TC.2011.200
Show More Cited By

Index Terms

Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip
1. Software and its engineering
  1. Software creation and management
    1. Software development techniques

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cover image ACM Conferences

EMSOFT '07: Proceedings of the 7th ACM & IEEE international conference on Embedded software

September 2007

304 pages

ISBN:9781595938251

DOI:10.1145/1289927

Program Chairs:
Christoph M. Kirsch
University of Salzburg
,
Reinhard Wilhelm
Saarland University

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 September 2007

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ESWEEK07

Sponsor:

ESWEEK07: Third Embedded Systems Week

September 30 - October 3, 2007

Salzburg, Austria

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Cited By

Wang YShao ZChan HLiu DGuan Y(2014)Memory-Aware Task Scheduling with Communication Overhead Minimization for Streaming Applications on Bus-Based Multiprocessor System-on-ChipsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2013.17225:7(1797-1807)Online publication date: 1-Jul-2014
https://dl.acm.org/doi/10.1109/TPDS.2013.172
Wang YLiu DQin ZShao Z(2013)Optimally Removing Intercore Communication Overhead for Streaming Applications on MPSoCsIEEE Transactions on Computers10.1109/TC.2011.23662:2(336-350)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TC.2011.236
Hsiu PHsieh CLee DKuo T(2012)Multilayer Bus Optimization for Real-Time Embedded SystemsIEEE Transactions on Computers10.1109/TC.2011.20061:11(1638-1650)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TC.2011.200
Marcon CCalazans NMoreno EMoraes FHessel FSusin A(2011)CAFESJournal of Parallel and Distributed Computing10.1016/j.jpdc.2010.10.00271:5(714-728)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1016/j.jpdc.2010.10.002
Chen YShih CKuo T(2010)Processing element allocation and dynamic scheduling codesign for multi-function SoCsReal-Time Systems10.1007/s11241-009-9090-944:1-3(72-104)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1007/s11241-009-9090-9
Lombardi MMilano MRuggiero MBenini L(2010)Stochastic allocation and scheduling for conditional task graphs in multi-processor systems-on-chipJournal of Scheduling10.1007/s10951-010-0184-y13:4(315-345)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1007/s10951-010-0184-y

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