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A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques

Published: 06 February 2008 Publication History

Abstract

Scan chains are popularly used as the channels for silicon testing and debugging. However, they have also been identified as one of the culprits of silicon failure more recently. To cope with this problem, several scan chain diagnosis approaches have been proposed in the past. The existing methods, however, suffer from one common drawback—that is, they rely on fault models and matching heuristics to locate the faults. Such a paradigm may run into difficulty when the fault under diagnosis does not match the fault model exactly, for example, when there is a bridging between a flip-flop and a logic cell, or the fault is temporal and only manifests itself intermittently. In light of this, we propose in this article a more versatile model-free paradigm for locating the faulty flip-flops in a scan chain, incorporating a number of signal processing techniques, such as filtering and edge detection. These techniques performed on the test responses of the failing chip under diagnosis directly can effectively reveal the fault location(s) in a scan chain. As compared to the previous works, our approach is better capable of handling intermittent faults and bridging faults, even under nonideal conditions, for example, when the core logic is also faulty. Experimental results on several real designs indicate that this approach can indeed catch some nasty faults that previous methods could not catch.

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Cited By

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  • (2012)On Diagnosis of Timing Failures in Scan ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.218629831:7(1102-1115)Online publication date: 1-Jul-2012
  • (2011)Diagnosing scan clock delay faults through statistical timing pruningProceedings of the 48th Design Automation Conference10.1145/2024724.2024823(423-428)Online publication date: 5-Jun-2011
  • (2011)Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic DefectsProceedings of the 2011 Asian Test Symposium10.1109/ATS.2011.61(297-302)Online publication date: 20-Nov-2011

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  1. A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques

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    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 13, Issue 1
    January 2008
    496 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/1297666
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 06 February 2008
    Accepted: 01 September 2007
    Revised: 01 April 2007
    Received: 01 September 2006
    Published in TODAES Volume 13, Issue 1

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    Author Tags

    1. Diagnosis
    2. design for testability
    3. fault
    4. profiling
    5. scan chain

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    View all
    • (2012)On Diagnosis of Timing Failures in Scan ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.218629831:7(1102-1115)Online publication date: 1-Jul-2012
    • (2011)Diagnosing scan clock delay faults through statistical timing pruningProceedings of the 48th Design Automation Conference10.1145/2024724.2024823(423-428)Online publication date: 5-Jun-2011
    • (2011)Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic DefectsProceedings of the 2011 Asian Test Symposium10.1109/ATS.2011.61(297-302)Online publication date: 20-Nov-2011

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