Abstract
Many real-time systems, such as battery-operated embedded devices, are energy constrained. A common problem for these systems is how to reduce energy consumption in the system as much as possible while still meeting the deadlines; a commonly used power management mechanism by these systems is dynamic voltage scaling (DVS). Usually, the workloads executed by these systems are variable and, more often than not, unpredictable. Because of the unpredictability of the workloads, one cannot guarantee to minimize the energy consumption in the system. However, if the variability of the workloads can be captured by the probability distribution of the computational requirement of each task in the system, it is possible to achieve the goal of minimizing the expected energy consumption in the system. In this paper, we investigate DVS schemes that aim at minimizing expected energy consumption for frame-based hard real-time systems. Our investigation considers various DVS strategies (i.e., intra-task DVS, inter-task DVS, and hybrid DVS) and both an ideal system model (i.e., assuming unrestricted continuous frequency, well-defined power-frequency relation, and no speed change overhead) and a realistic system model (i.e., the processor provides a set of discrete speeds, no assumption is made on power-frequency relation, and speed change overhead is considered). The highlights of the investigation are two practical DVS schemes: Practical PACE (PPACE) for a single task and Practical Inter-Task DVS (PITDVS2) for general frame-based systems. Evaluation results show that our proposed schemes outperform and achieve significant energy savings over existing schemes.
- AbouGhazaleh, N., Mossé, D., Childers, B., Melhem, R., and Craven, M. 2003. Collaborative operating system and compiler power management for real-time applications. In Proceedings of IEEE Real-Time Embedded Technology and Applications Symposium (RTAS). Google Scholar
- AMD. 2001. Mobile AMD Athlon 4 Processor Model 6 CPGA data sheet. http://www.amd.com.Google Scholar
- Austin, T., Larson, E., and Ernst, D. 2002. Simplescalar: An infrastructure for computer system modeling. IEEE Comput. 35, 2, 59--67. Google Scholar
- Aydin, H., Melhem, R., Mossé, D., and Mejia-Alvarez, P. 2001. Dynamic and aggressive scheduling techniques for power-aware real-time systems. In Proceedings of IEEE Real-Time Systems Symposium (RTSS). 95--105. Google Scholar
- Baker, T. P. and Shaw, A. 1989. The cyclic executive model and ada. Real-Time Syst. J. 1, 1, 7--26.Google Scholar
- Brooks, D., Bose, P., Schuster, S., Jacobson, H., Kudva, P., Buyuktosunoglu, A., Wellman, J., Zyuban, V., Gupta, M., and Cook, P. 2000. Power-aware microarchitecture: Design and modeling challenges for next generation microprocessors. IEEE Micro 20, 6. Google Scholar
- Burd, T. and Brodersen, R. 2000. Design issues for dynamic voltage scaling. In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED). Google Scholar
- Contreras, G. and Martonosi, M. 2005. Power prediction for intel xscale processors using performance monitoring unit eventss. In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED). Google Scholar
- Cormen, T., Leiserson, C., Rivest, R., and Stein, C. 2001. Introduction to Algorithms. MIT Press, Cambridge, MA. Google Scholar
- Ernst, R. and Ye, W. 1997. Embedded program timing analysis based on path clustering and architecture classification. In Proceedings of International Conference on Computer Aided Design (ICCAD). San Jose, CA. Google Scholar
- Gruian, F. 2001a. Hard real-time scheduling for low-energy using stochastic data and dvs processors. In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED). Google Scholar
- Gruian, F. 2001b. On energy reduction in hard real-time systems containing tasks with stochastic execution times. In Proceedings of IEEE Workshop on Power Management for Real-Time and Embedded Systems. Taipei, Taiwan.Google Scholar
- Gruian, F. and Kuchcinski, K. 2003. Uncertainty-based scheduling: energy efficient ordering for tasks with variable execution time. In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED). Seoul, Korea. Google Scholar
- Hong, I., Qu, G., Potkonjak, M., and Srivastava, M. 1998. Synthesis techniques for low-power hard real-time systems on variable voltage processors. In Proceedings of IEEE Real-Time Systems Symposium (RTSS). Madrid, Spain. Google Scholar
- Hsu, C. and Kremer, U. 2003. The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction. In Proceedings of ACM Programming Language Design and Implementation (PLDI). Google Scholar
- Ishihara, T. and Yasuura, H. 1998. Voltage scheduling problem for dynamically variable voltage processors. In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED). 197--202. Google Scholar
- Kim, W., Shin, D., Yun, H., Kim, J., and Min, S. 2002. Performance comparison of dynamic voltage scaling algorithms for hard real-time systems. In Proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). Google Scholar
- Krantz, S., Kress, S., and Kress, R. 1999. Jensen's Inequality. Birkhauser.Google Scholar
- Lang, S. 1973. Calculus of Several Variables. Addison-Wesley, Reading, MA.Google Scholar
- Lorch, J. 2001. Operating systems techniques for reducing processor energy consumption. Ph.D. thesis, University of California at Berkeley. Google Scholar
- Lorch, J. and Smith, A. 2001. Improving dynamic voltage scaling algorithms with PACE. In Proceedings of ACM SIGMETRICS. Google Scholar
- Lorch, J. and Smith, A. 2003. Operating system modifications for task-based speed and voltage scheduling. In Proceedings of International Conference on Mobile Systems, Applications, and Services (MobiSys). Google Scholar
- Lorch, J. and Smith, A. 2004. PACE: a new approach to dynamic voltage scaling. IEEE Trans. Comput. 53, 7, 856--869. Google Scholar
- Mahalanobis, A., Kumar, B. V. K. V., and Sims, S. 1996. Distance-classifier correlation filters for multiclass target recognition. Appl. Optics 35.Google Scholar
- Miyoshi, A., Lefurgy, C., Hensbergen, E. V., Rajamony, R., and Rajkumar, R. 2002. Critical power slope: Understanding the runtime effects of frequency scaling. In Proceedings of the 16th ACM International Conference on Supercomputing. Google Scholar
- Mochocki, B., Hu, X., and Quan, G. 2004. A unified approach to variable voltage scheduling for nonideal dvs processors. IEEE Trans. Comput.-Aid. Design Integrat. Circ. Syst. 23, 9, 1370--1377. Google Scholar
- Mossé, D., Aydin, H., Childers, B., and Melhem, R. 2000. Compiler-assisted dynamic power-aware scheduling for real-time applications. In Proceedings of Workshop on Compiler and OS for Low Power (COLP).Google Scholar
- Pillai, P. and Shin, K. G. 2001. Real-time dynamic voltage scaling for low-power embedded operating systems. In Proceedings of ACM Symposium on Operating Systems Principles (SOSP). 89--102. Google Scholar
- Preparata, F. and Shamos, M. 1993. Computational Geometry An Introduction. Springer. Google Scholar
- Ramamritham, K. and Stankovic, J. 1994. Scheduling algorithms and operating systems support for real-time systems. In Proceedings of the IEEE.Google Scholar
- Rusu, C., Xu, R., Melhem, R., and Mossé, D. 2004. Energy-efficient policies for request-driven soft real-time systems. In Proceedings of Euromicro Conference on Real-Time Systems (ECRTS). Catania, Italy. Google Scholar
- Saewong, S. and Rajkumar, R. 2003. Practical voltage-scaling for fixed-priority RT-systems. In Proceedings of IEEE Real-Time Embedded Technology and Applications Symposium (RTAS). Google Scholar
- Seo, J., Kim, T., and Dutt, N. 2005. Optimal Integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. In Proceedings of International Conference on Computer Aided Design (ICCAD). Google Scholar
- Shin, D., Kim, J., and Lee, S. 2001. Intra-task voltage scheduling for low-energy hard real-time applications. IEEE Design Test Comput. 18, 23. Google Scholar
- Sinha, A. and Chandrakasan, A. 2001. Dynamic voltage scheduling using adaptive filtering of workload traces. In Proceedings of International Conference on VLSI Design (VLSID). Google Scholar
- Transmeta 2005. Crusoe processor specification. http://www.transmeta.com/crusoe/specs.html.Google Scholar
- Weste, N. and Eshraghian, K. 1993. Principles of CMOS VLSI Design. Addison-Wesley, Reading, MA. Google Scholar
- Xie, F., Martonosi, M., and Malik, S. 2003. Compile-time dynamic voltage scaling settings: Opportunities and limits. In Proceedings of Programming Language Design and Implementation (PLDI). Google Scholar
- Xscale 2007. Intel XScale Microarchitecture. http://developer.intel.com/design/intelxscale/.Google Scholar
- Xscalepower 2005. Intel XScale Microarchitecture:benchmarks. http://web.archive.org/web/20050326232506/http://developer.intel.com/design/intelxscale/benchmarks.htm.Google Scholar
- Xu, R., Mossé, D., and Melhem, R. 2005. Minimizing expected energy in real-time embedded systems. In Proceedings of ACM International Conference on Embedded Software (EMSOFT). Jersey City, New Jersey. Google Scholar
- Xu, R., Xi, C., Melhem, R., and Mossé, D. 2004. Practical PACE for embedded systems. In Proceedings of ACM International Conference on Embedded Software (EMSOFT). Pisa, Italy. Google Scholar
- Yao, F., Demers, A., and Shankar, S. 1995. A scheduling model for reduced CPU energy. In Proceedings of IEEE Annual Foundations of Computer Science (FOCS). 374--382. Google Scholar
- Yuan, W. and Nahrstedt, K. 2003. Energy-efficient soft real-time CPU scheduling for mobile multimedia systems. In Proceedings of ACM Symposium on Operating Systems Principles (SOSP). Google Scholar
- Zhang, Y., Lu, Z., Lach, J., Skadron, K., and Stan, M. 2005. Optimal procrastinating voltage scheduling for hard real-time systems. In Proceedings of Desing Automation Conference (DAC). Google Scholar
- Zhu, Y. and Mueller, F. 2004. Feedback EDF scheduling exploiting dynamic voltage scaling. In Proceedings of IEEE Real-Time Embedded Technology and Applications Symposium (RTAS). Toronto, Canada. Google Scholar
Index Terms
- Minimizing expected energy consumption in real-time systems through dynamic voltage scaling
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