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A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs

Published: 16 September 2007 Publication History

Abstract

Chip Multiprocessor (CMP) architectures are the principal trend in current and future microprocessor design, and on-chip shared cache mechanisms play a key role to realize low-power and high performance CMPs. In this paper, we propose a way-allocatable shared cache mechanism, which can achieve both high performance and cache power reduction by using cache partitioning and power gating. We evaluate the performance of our cache mechanism by a cycle accurate simulator, in terms of performance and energy consumption. The performance evaluation results show that the proposed mechanism can properly adjust the control policy from a performance-oriented configuration to a energy-oriented one. The proposed cache mechanism with a performance-oriented parameter setting can reduce energy consumption by 20% while keeping the performance, and the cache with an energy-oriented parameter setting can reduce 54% energy consumption with a performance degradation of 13%.

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  • (2012)Survey of scheduling techniques for addressing shared resources in multicore processorsACM Computing Surveys (CSUR)10.1145/2379776.237978045:1(1-28)Online publication date: 7-Dec-2012
  • (2008)Modeling of cache access behavior based on Zipf's lawProceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture10.1145/1509084.1509086(9-15)Online publication date: 26-Oct-2008

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cover image ACM Conferences
MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
September 2007
113 pages
ISBN:9781595938077
DOI:10.1145/1327171
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 16 September 2007

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View all
  • (2016)Computer System Design Exploration Using Local Search and Genetic Algorithms2016 4th Intl Conf on Applied Computing and Information Technology/3rd Intl Conf on Computational Science/Intelligence and Applied Informatics/1st Intl Conf on Big Data, Cloud Computing, Data Science & Engineering (ACIT-CSII-BCD)10.1109/ACIT-CSII-BCD.2016.045(189-195)Online publication date: Dec-2016
  • (2012)Survey of scheduling techniques for addressing shared resources in multicore processorsACM Computing Surveys (CSUR)10.1145/2379776.237978045:1(1-28)Online publication date: 7-Dec-2012
  • (2008)Modeling of cache access behavior based on Zipf's lawProceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture10.1145/1509084.1509086(9-15)Online publication date: 26-Oct-2008

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