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FPGA-optimised high-quality uniform random number generators

Published: 24 February 2008 Publication History

Abstract

This paper introduces a method of constructing random numbergenerators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. The construction methodis designed to ensure maximum clock rates, while using the minimum of resources, and providing statistical quality at the level of the best software generators. In all platforms tested, the generators are limited in speed only by the clock distribution network or the maximum clockspeed of the underlying RAM primitives, using a platform independent VHDL description with no placement or other hints. The area utilisation is also very low, with a Virtex-5 generator requiring just one Block-RAMand 41 slices to produce 48Gb/s at 550MHz: over 14 times faster than the commonly used Mersenne-Twister RNG on an Opteron at 2.2GHz, while providing the same level of quality

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  • (2023)A Linear Recurrence-Based Pseudorandom Number Generator Optimized for Detector EmulatorsIEEE Transactions on Nuclear Science10.1109/TNS.2023.328525170:8(2139-2147)Online publication date: Aug-2023
  • (2022)A brief and understandable guide to pseudo-random number generators and specific models for securityStatistics Surveys10.1214/22-SS13616:noneOnline publication date: 1-Jan-2022
  • (2017)A memory optimized mersenne-twister random number generator2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8053004(639-642)Online publication date: Aug-2017
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    cover image ACM Conferences
    FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
    February 2008
    278 pages
    ISBN:9781595939340
    DOI:10.1145/1344671
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 24 February 2008

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    Author Tags

    1. generation
    2. number
    3. random

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    View all
    • (2023)A Linear Recurrence-Based Pseudorandom Number Generator Optimized for Detector EmulatorsIEEE Transactions on Nuclear Science10.1109/TNS.2023.328525170:8(2139-2147)Online publication date: Aug-2023
    • (2022)A brief and understandable guide to pseudo-random number generators and specific models for securityStatistics Surveys10.1214/22-SS13616:noneOnline publication date: 1-Jan-2022
    • (2017)A memory optimized mersenne-twister random number generator2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8053004(639-642)Online publication date: Aug-2017
    • (2013)The LUT-SR family of uniform random number generators for FPGA architecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219417121:4(761-770)Online publication date: 1-Apr-2013
    • (2013)A Mersenne Twister Hardware Implementation for the Monte Carlo Localization AlgorithmJournal of Signal Processing Systems10.1007/s11265-012-0661-y70:1(75-85)Online publication date: 1-Jan-2013
    • (2011)FPGA Based Reconfigurable Computing Systems: A New Design Approach - A ReviewAdvanced Materials Research10.4028/www.scientific.net/AMR.403-408.4272403-408(4272-4278)Online publication date: Nov-2011
    • (2010)Design of visual based-FPGA Ping-Pang game with multi-models2010 Second Pacific-Asia Conference on Circuits, Communications and System10.1109/PACCS.2010.5626899(31-34)Online publication date: Aug-2010
    • (2009)FPGA-driven pseudorandom number generators aimed at accelerating Monte Carlo methods2009 IEEE/ACS International Conference on Computer Systems and Applications10.1109/AICCSA.2009.5069452(989-996)Online publication date: May-2009
    • (2008)FPGA acceleration of quasi-Monte Carlo in finance2008 International Conference on Field Programmable Logic and Applications10.1109/FPL.2008.4629954(335-340)Online publication date: Sep-2008
    • (2008)Resource efficient generators for the floating-point uniform and exponential distributionsProceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2008.4580162(102-107)Online publication date: 2-Jul-2008

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