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As CPUs rely increasingly on parallelism rather than frequency to improve performance, the memory system emerges as the fundamental barrier to continued improvement in system-level performance. Previous tactics like increasing cache size and associativity become less and less relevant in a world where NUMA memory behaviors and inter-processor contention dominate application performance. MSPC is a forum for exploring these emerging challenges.
When we accepted the task of organizing this year's MSPC, we did so with the belief that the memory systems community needed a forum that relaxed the constraints of the research conference format to allow for the exploration of ideas that were too immature or controversial for a full research conference. We further saw this workshop as a critical opportunity to build a community among researchers interested in memory systems. With these objectives in mind, we implemented some significant format changes this year, with the intention of making MSPC less of a mini-conference and more of a place where the freshest and most surprising ideas in this field can be explored with energy and candor. In lieu of the program of ten-page technical papers that MSPC has used in the past, this year we solicited five-page position papers as well as two-page position abstracts. Our goals in doing so were both to permit creation of a viable submission from less mature research, and also to make it easier to recognize the delta in the common case that an MSPC paper is followed by a full conference publication. These changes were motivated in part from experience with HotOS.
We received 26 submissions, including 22 five-page position papers and four position abstracts. Each position paper received at least five reviews. The program committee met via teleconference on December 20, 2007. In keeping with the goals of the new format, the program committee aimed to accept position papers that provided both a clear problem statement and some quantitative exploration of the solution space, with the understanding that these would lack the completeness and depth of exploration expected of a full-conference submission. Position papers that presented a problem but lacked an exploration of the solution space were generally not acceptable to the committee, although the two-page position abstract format was more amenable to such submissions. In addition to presentations of the position papers included in this volume, the workshop will also included a panel discussion on "The Next Solution" and a Wild and Crazy Ideas session.
Proceeding Downloads
General and efficient locking without blocking
Standard concurrency control mechanisms offer a trade-off: Transactional memory approaches maximize concurrency, but suffer high overheads and cost for retrying in the case of actual contention. Locking offers lower overheads, but typically reduces ...
Concurrency control with data coloring
Concurrency control is one of the main sources of error and complexity in shared memory parallel programming. While there are several techniques to handle concurrency control such as locks and transactional memory, simplifying concurrency control has ...
The potential for variable-granularity access tracking for optimistic parallelism
Support for optimistic parallelism such as thread-level speculation (TLS) and transactional memory (TM) has been proposed to ease the task of parallelizing software to exploit the new abundance of multicores. A key requirement for such support is the ...
Reasoning about the ARM weakly consistent memory model
This paper describes a formalization of the ARM weakly consistent memory model: the architectural contract between parallel programs and shared memory multiprocessor implementations. We claim that a clean, unambiguous, and mechanically verifiable ...
IWannaBit!
Just One Lousy Bit! I want to know if any memory operation misses or any line in my L1 cache gets evicted. Why? Because with this one Bit I can write any number of lock-free algorithms easily. This Bit gives me an N-word atomic read set, and with a ...
What can performance counters do for memory subsystem analysis?
Nowadays, all major processors provide a set of performance counters which capture micro-architectural level information, such as the number of elapsed cycles, cache misses, or instructions executed. Counters can be found in processor cores, processor ...
The case for simple, visible cache coherency
The shared memory research community has proposed many complex communication protocols that aim to eliminate specific performance bottlenecks, while still providing an easy-to-use communication interface. Although tailored protocols can eliminate some ...
GC assertions: using the garbage collector to check heap properties
This paper introduces GC assertions, a system interface that programmers can use to check for errors, such as data structure invariant violations, and to diagnose performance problems, such as memory leaks. GC assertions are checked by the garbage ...
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Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
MSPC '14 | 20 | 6 | 30% |
Overall | 20 | 6 | 30% |