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The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk

Published: 05 April 2008 Publication History

Abstract

With deep submicron technologies, the importance of interconnect parasitics on delay and noise has been an ever increasing trend. Consequently the variation in interconnect parameters have a larger impact on final timing and functional yield of the product. We present a comprehensive analysis to quantify the impact of parametric variations on the reliability of global interconnect links in the presence of crosstalk. The impact of parametric variations on wire delay and crosstalk noise is studied for a global interconnect structure in 90nm UMC technology, followed by a novel technique to estimate the bit error rate (BER) of such links. This methodology is employed to explore the design space of interconnect channels in order to mitigate the impact of variability.

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    cover image ACM Conferences
    SLIP '08: Proceedings of the 2008 international workshop on System level interconnect prediction
    April 2008
    104 pages
    ISBN:9781595939180
    DOI:10.1145/1353610
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 05 April 2008

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    Author Tags

    1. Bit Error Rate(BER)
    2. cross-talk
    3. interconnect
    4. variability

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    View all
    • (2018)A Primer on Cryptographic Primitives and Security AttacksPhysically Unclonable Functions10.1007/978-3-319-76804-5_1(1-15)Online publication date: 19-Apr-2018
    • (2011)Power - Reliability tradeoff in low power 4-PAM signaling in on-chip communication2011 3rd Asia Symposium on Quality Electronic Design (ASQED)10.1109/ASQED.2011.6111711(109-114)Online publication date: Jul-2011
    • (2011)Statistical analysis of crosstalk-induced errors for on-chip interconnectsIET Computers & Digital Techniques10.1049/iet-cdt.2009.00545:2(104)Online publication date: 2011
    • (2010)Statistical guarantees of performance for MIMO designs2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN)10.1109/DSN.2010.5544281(467-476)Online publication date: Jun-2010
    • (2009)A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis2009 IEEE Student Conference on Research and Development (SCOReD)10.1109/SCORED.2009.5443278(97-100)Online publication date: Nov-2009

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