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Rent's rule and parallel programs: characterizing network traffic behavior

Published: 05 April 2008 Publication History

Abstract

In VLSI systems, Rent's rule characterizes the locality of interconnect between different subsystems, and allows an efficient layout of the circuit on a chip. With rising complexities of both hardware and software, Systems-on-Chip are converging to multiprocessor architectures connected by a Network-on-Chip. Here, packets are routed instead of wires, and threads of a parallel program are distributed among processors. Still, Rent's rule remains applicable, as it can now be used to describe the locality of network traffic. In this paper, we analyze network traffic on an on-chip network and observe the power-law relation between the size of clusters of network nodes and their external bandwidths. We then use the same techniques to study the time-varying behavior of the application, and derive the implications for future on-chip networks.

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    cover image ACM Conferences
    SLIP '08: Proceedings of the 2008 international workshop on System level interconnect prediction
    April 2008
    104 pages
    ISBN:9781595939180
    DOI:10.1145/1353610
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    Published: 05 April 2008

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    Author Tags

    1. Rent's rule
    2. characterization
    3. locality
    4. network traffic behavior
    5. network-on-chip

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    Cited By

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    • (2021)The Path to Successful Wafer-Scale Integration: The Cerebras StoryIEEE Micro10.1109/MM.2021.311202541:6(52-57)Online publication date: 1-Nov-2021
    • (2018)Vertical Arbitration-Free 3-D NoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.276841537:9(1853-1866)Online publication date: 1-Sep-2018
    • (2017)Extending the Performance of Hybrid NoCs beyond the Limitations of Network HeterogeneityJournal of Low Power Electronics and Applications10.3390/jlpea70200087:2(8)Online publication date: 26-Apr-2017
    • (2017)An energy-aware mapping algorithm for mesh-based network-on-chip architectures2017 International Conference on Progress in Informatics and Computing (PIC)10.1109/PIC.2017.8359572(357-361)Online publication date: Dec-2017
    • (2016)SlideAcross: A Low-Latency Adaptive Router for Chip Multi-processor2016 Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2016.40(115-122)Online publication date: Aug-2016
    • (2016)Design and dynamic management of hierarchical NoCsMicroprocessors & Microsystems10.1016/j.micpro.2015.09.00440:C(154-166)Online publication date: 1-Feb-2016
    • (2015)Unbiased Regional Congestion Aware Selection Function for NoCsProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2786574(1-8)Online publication date: 28-Sep-2015
    • (2015)Locality-Aware Network Utilization Balancing in NoCsACM Transactions on Design Automation of Electronic Systems10.1145/274301221:1(1-26)Online publication date: 2-Dec-2015
    • (2015)Multicast On-chip Traffic Analysis Targeting Manycore NoC DesignProceedings of the 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing10.1109/PDP.2015.26(370-378)Online publication date: 4-Mar-2015
    • (2015)Parametric hierarchical mesh interconnected structure for Network-on-Chip2015 6th IEEE International Conference on Software Engineering and Service Science (ICSESS)10.1109/ICSESS.2015.7339035(193-197)Online publication date: Sep-2015
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