Hosung (Leo) Kim
ABSTRACT
It is well known that optimizations made by traditional logic synthesis tools often correlate poorly with post-layout performance; this is largely a result of interconnect effects only visible after layout. As a result, several attempts at physically aware logic synthesis have been made (e.g.,[2], [9], [14], [4], [7], [12], [16], [15]). In this paper a corrective methodology is proposed for timing-driven logic restructuring at the placement level; the approach currently focuses on LUT-based FPGAs.
Driven by placement level static timing analysis, the method induces relatively large, timing-critical fan-in trees via (temporary) replication as in [9]. Such trees are then reimplemented where the degrees of freedom include functional decomposition of LUTs, subject graph covering/mapping, and physical embedding. A dynamic programming algorithm optimizes over all of these freedoms simultaneously. All simple disjoint decompositions (i.e., Ashenhurst style) are encoded in the subject tree/graph using choice nodes similar to those in [11]. At the same time, because embedding is done simultaneously, interconnect delay is directly taken into account
We have implemented the framework and in many cases we were able to approach a fixed flip-flop lower-bound on achievable clock period. Promising experimental results are reported with average 14.8% (up to 37.4%) clock period reduction compared with the timing-driven placement from VPR [13] and average 6.6% (upto 17%) reduction compared with the basic fan-in tree embedder from [9].
- Ashenhurst, R. L.: The decomposition of switching functions. The annals of the Harvard computation laboratory, XXIX:74--116, 1959.Google Scholar
- G. Beraudo and J. Lillis. Timing optimization of FPGA placements by logic replication. In Proc. of ACM/IEEE DAC, pages 196--201, June 2003. Google ScholarDigital Library
- K. C. Chen, J. Cong, Y. Ding, A. Kahng, and P. Trajmar. DAG-map: graph-based FPGA technology mapping for delay optimization. IEEE Design & Test, pages 7--20, Sept. 1992. Google ScholarDigital Library
- G. Chen and J. Cong. Simultaneous timing-driven placement and duplication. In Proc. of ISFPGAs, pages 51--59, Feb. 2005. Google ScholarDigital Library
- J. Cong, Y. Ding, An optimal technology mapping algorithm for delay minimization in lookup-table based FPGA designs, ICCAD, 1992. Google ScholarDigital Library
- R. J. Francis, J. Rose, Z. Vranesic, Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGA, DAC, 1991. Google ScholarDigital Library
- H. Kim, J. Lillis, and M. Hrkić. Techniques for Improved Placement Coupled Logic Replication. GLSVLSI, 2006. Google ScholarDigital Library
- Kohavi, Z.: Switching and Finite Automata Theory. McGraw-Hill Book Company, 1978. Google ScholarDigital Library
- M. Hrkić, J. Lillis, and G. Beraudo. An approach to placement-coupled logic replication. IEEE TCAD, vol. 20, issue 11, 2006. Google ScholarDigital Library
- Y. Kukimoto, R. Brayton, and P. Sawkar. Delay-optimal technology mapping by DAG covering. In DAC, 1998. Google ScholarDigital Library
- E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness. Logic decomposition during technology mapping, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 16(8):813--834, August 1997. Google ScholarDigital Library
- J. Lin, A. Jagannathan, and J. Cong, Placement-Driven Technology Mapping for LUT-Based FPGAs, ISFPGAs, 2003. Google ScholarDigital Library
- A. Marquardt, V. Betz, and J. Rose. Timing-driven placement for FPGAs. In ISFPGAs, 2000. Google ScholarDigital Library
- K. Schabas and S. D. Brown. Using logic duplication to improve performance in FPGAs. In Proc. of ISFPGAs, 2003. Google ScholarDigital Library
- D. Singh, S. Brown, An area-efficient timing closure technique for FPGAs using Shannon's expansion, Integration, the VLSI Journal, vol. 40, Issue 2, Feb. 2007. Google ScholarDigital Library
- P. Suaris, L. Liu, Y. Ding, N. Chou, Incremental Physical Resynthesis for Timing Optimization, ISFPGAs, 2004. Google ScholarDigital Library
- A. Srivastava, R. Kastner, and M. Sarrafzadeh. Timing driven gate duplication: Complexity issues and algorithms. In Proc. of ICCAD, 2000. Google ScholarDigital Library
Index Terms
- A framework for layout-level logic restructuring
Recommendations
A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs
It is well known that optimizations made by traditional logic synthesis tools often correlate poorly with post-layout performance; this is largely a result of interconnect effects only being visible after layout. In this paper, a corrective methodology ...
ITOP: integrating timing optimization within placement
ISPD '10: Proceedings of the 19th international symposium on Physical designTiming-driven placement is a critical step in nanometer-scale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a commonly used technique. This paper shows that such an approach can ...
Crosstalk- and performance-driven multilevel full-chip routing
In this paper, we propose a novel framework for fast multilevel routing considering crosstalk and performance optimization. To handle the crosstalk minimization problem, we incorporate an intermediate stage of layer/track assignment into the multilevel ...
Comments