research-article

Future generation supercomputers II: a paradigm for cluster architecture

Authors:

N. Venkateswaran,

Deepak Srinivasan,

Madhavan Manivannan,

T P Ramnath Sai Sagar,

Shyamsundar Gopalakrishnan,

VinothKrishnan Elangovan,

Prem Kumar Ramesh,

Karthik Ganesan,

Viswanath Krishnamurthy,

SivaramakrishnanAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 35, Issue 5

Pages 61 - 70

https://doi.org/10.1145/1360464.1360467

Published: 01 December 2007 Publication History

Abstract

In part-I, a novel multi-core node architecture was proposed which when employed in a cluster environment would be capable of tackling computational complexity associated with wide class of applications. Furthermore, it was discussed that by appropriately scaling the architectural specifications, Teraops computing power could be achieved at the node level. In order to harness the computational power of such a node, we have developed an efficient application execution model with a competent cluster architectural backbone. In this paper we present the novel cluster paradigm, dealing with operating system design, parallel programming model and cluster interconnection network. Our approach in developing the competent cluster design revolves around an execution model to aid the execution of multiple applications simultaneously on all partitions of the cluster, leading to cost sharing across applications. This would be a major initiative towards achieving Cost-Effective Supercomputing.

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Cited By

Venkateswaran NSrinivasan DManivannan MSai Sagar TGopalakrishnan SElangovan VChandrasekar KRamesh PVenkatesan VBabu ASudharshan (2007)Future generation supercomputers IACM SIGARCH Computer Architecture News10.1145/1360464.136046635:5(49-60)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1145/1360464.1360466

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 35, Issue 5

Special issue: ALPS '07---advanced low power systems

December 2007

73 pages

ISSN:0163-5964

DOI:10.1145/1360464

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Copyright © 2007 Authors.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 December 2007

Published in SIGARCH Volume 35, Issue 5

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Cited By

Venkateswaran NSrinivasan DManivannan MSai Sagar TGopalakrishnan SElangovan VChandrasekar KRamesh PVenkatesan VBabu ASudharshan (2007)Future generation supercomputers IACM SIGARCH Computer Architecture News10.1145/1360464.136046635:5(49-60)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1145/1360464.1360466

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