Nei-Chiung Perng
Tei-Wei Kuo
ABSTRACT
To minimize the hardware fabrications in reconfigurable devices, this paper explores hardware synthesis to derive reconfiguration plans during the design time based on schedules derived by CAD tools, where a schedule includes the starting time, the execution time, and the intertask data transmissions for each task. We propose scheduling algorithms to derive optimal solutions for hardware descriptions with the same reconfiguration latency based on backward configuration and backward ordering strategies. For general cases, where a hardware description might be shared by tasks, we develop an algorithm based on a duplication merging strategy with performance evaluations. Our proposed algorithms could be applied after the hardware/software co-design procedures of task partitioning and scheduling to optimize the hardware requirements during the design time.
- S. Banerjee, E. Bozorgzadeh, and N. D. Dutt. Physically-aware hw-sw partitioning for reconfigurable architectures with partial dynamic reconfiguration. In DAC, pages 335--340, 2005. Google Scholar
Digital Library
- G. De Micheli and R. K. Gupta. Hardware/software co-design. Proceedings of the IEEE, 85(3): 349--365, Mar 1997.Google ScholarCross Ref
- A. DeHon and J. Wawrzynek. Reconfigurable computing: What, why, and implicatios for design automation. In the 36th ACM/IEEE Conference on Design Automation, pages 610--615, 1999. Google ScholarDigital Library
- R. P. Dick, D. L. Rhodes, and W. Wolf. TGFF: Task graphs for free. In Proc. Int. Workshop Hardware/Software Codesign, 1998. Google ScholarDigital Library
- S. H. Gerez. Algorithms for VLSI design Automation. John Wiley & Sons, 1999. Google ScholarDigital Library
- S. Ghiasi, A. Nahapetian, and M. Sarrafzadeh. An optimal algorithm for minimizing run-time reconfiguration delay. ACM Transactions on Embedded Computing Systems, 3(2): 237--256, May 2004. Google ScholarDigital Library
- J. Harkin, T. M. McGinnity, and L. P. Maguire. Partitioning methodology for dynamically reconfigurable embedded systems. IEE Proceedings on Computers and Digital Techniques, 147(6): 391--396, Nov 2000.Google ScholarCross Ref
- J. Harkin, T. M. McGinnity, and L. P. Maguire. Modeling and optimizing run-time reconfiguration using evolutionary computation. ACM Transactions on Embedded Computing Systems, 3(4): 661--685, Nov 2004. Google ScholarDigital Library
- S. Hauck. Configuration prefetch for single context reconfigurable coprocessors. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 65--74, 1998. Google ScholarDigital Library
- S. Hauck. The roles of FPGAs in reprogrammable systems. In Proceedings of the IEEE, pages 615--638, 1998.Google ScholarCross Ref
- J. Noguera and R. M. Badia. Multitasking on reconfigurable architectures: Microarchitecture support and dynamic scheduling. ACM Transactions on Embedded Computing Systems, 3(2): 385--406, May 2004. Google ScholarDigital Library
- S. Singh and P. James-Roxby. Lava and JBits: From HDL to Bitstream in seconds. In IEEE Symposium on FPGAs for Custom Computing Machines, pages 91--100, Apr 2001. Google ScholarDigital Library
- D. B. West. Introduction to Graph Theory. Prentice-Hall, Inc., 2/e edition, 2001.Google Scholar
- Xilinx. XAPP151 Virtex Series Configuration Architecture User Guide, (vl.7) edition, Oct 2004.Google Scholar
- P.-H. Yuh, C.-L. Yang, and Y.-W. Chang. Temporal floorplanning using the t-tree formulation. In ICCAD, pages 300--305, 2004. Google ScholarDigital Library
Index Terms
- The minimization of hardware size in reconfigurable embedded platforms
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