ABSTRACT
Sub-threshold leakage in SRAM based cache memories is becoming a predominant source of power consumption in deep-sub micron CMOS designs. Phase Change Random Access Memory (PRAM), a high density, fast access, non-volatile memory is being considered as a candidate for future universal memory technologies. In this paper, we investigate the architectural challenges in integrating a PRAM based memory into the conventional cache hierarchy. First, we develop PRAM cache delay and energy models. We then propose a hybrid PRAM architecture for L1 instruction caches on embedded processors. We also propose a PRAM based unified cache architecture for L2 caches on high-end microprocessors. Finally, we evaluate the proposed architectures, in terms of area, performance, and energy. The experimental results show that the PRAM based cache architectures achieve close to 80% reduction in the leakage energy consumption of a L1-L2 cache hierarchy.
- International technology roadmap for semiconductors, 2006 report. http:http://www.itrs.net/reports.html.Google Scholar
- D. Burger and T. M. Austin. The simplescalar tool set, version 2.0. SIGARCH Comput. Archit. News, 25(3):13--25, 1997. Google ScholarDigital Library
- K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy caches: simple techniques for reducing leakage power. In ISCA '02: Proceedings of the 29th annual international symposium on Computer architecture, pages 148--157, Washington, DC, USA, 2002. IEEE Computer Society. Google ScholarDigital Library
- D.--H. Kang, D.--H. Ahn, K.--B. Kim, J.F.Webb, and K.--W. Yi. One--dimensional heat conduction model for an electrical phase change random access memory device with an 8f2 memory cell(f=0:15¹m). Journal of Applied Physics, 94(5):3536--3542, 2003.Google ScholarCross Ref
- C. Lee, M. Potkonjak, and W. H. Mangione--Smith. Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems. In International Symposium on Microarchitecture, pages 330--335, 1997. Google ScholarDigital Library
- M. C. Merten, A. R. Trick, and R. D. Barnes. An architectural framework for runtime optimization. IEEE Trans. Comput., 50(6):567--589, 2001. Google ScholarDigital Library
- M. Powell, S.--H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar. Gated Vdd: A circuit technique to reduce leakage in deep--submicron cache memories. pages 90--95. Google ScholarDigital Library
- L. S and L. T. Oum -- a 180 nm nonvolatile memory cell element technology for stand alone and embedded applications. Electron Devices Meeting, 2001. IEDM Technical Digest. International, pages 36.5.1--36.5.4, 2001.Google Scholar
- S.Hudgens and B.Johnson. Overview of phase--change chalcogenide nonvolatile memory technology. Materials Research Society Bulletin, 2004., pages 829--832, 2004.Google ScholarCross Ref
- N. Takaura, M. Terao, K. Kurotsuchi, T. Yamauchi, O. Tonomura, Y. Hanaoka, R. Takemura, K. Osada, T. Kawahara, and H. Matsuoka. A gesbte phase--change memory cell featuring a tungsten heater electrode for low--power, highly stable, and short--read--cycle operations. Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International, pages 37.2.1--37.2.4, 8--10 Dec. 2003.Google ScholarCross Ref
- N. Wilton, S.J.E.; Jouppi. Cacti: an enhanced cache access and cycle time model. Solid--State Circuits, IEEE Journal of, 31(5):677--688, May 1996.Google Scholar
Index Terms
- A low-power phase change memory based hybrid cache architecture
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