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Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms

Published: 04 May 2008 Publication History

Abstract

This paper proposes a new method to estimate static power dissipation in digital circuits by evaluating simultaneously subthreshold and gate oxide leakage currents. The estimation method is performed over logic cells, including CMOS complex gates with multi-level series-parallel devices. Experimental results have been carried out on different fabrications processes, and good correlation with HSPICE simulator was obtained at cell and circuit levels. The algorithm presents a speed up of 80x when compared to HSPICE.

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  • (2009)Routing resistance influence in loading effect on leakage analysisProceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-11802-9_36(317-325)Online publication date: 9-Sep-2009

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    cover image ACM Conferences
    GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI
    May 2008
    480 pages
    ISBN:9781595939999
    DOI:10.1145/1366110
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    Published: 04 May 2008

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    Author Tags

    1. cmos gates
    2. leakage estimation
    3. logic design

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    May 4 - 6, 2008
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    • (2009)Routing resistance influence in loading effect on leakage analysisProceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-11802-9_36(317-325)Online publication date: 9-Sep-2009

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