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12bits 40mhz pipelined ADC with duty-correction circuit

Published: 04 May 2008 Publication History

Abstract

In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a 0.18µm CMOS n-well 1-poly 6-metal process and dissipates 184mW at 1.8V single supply. The SNDR of the proposed 12bit ADC is 52dB and SFDR of 59dBc (@Fs=20MHz, Fin=1MHz) is measured.

References

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S. Karthikeyan, "Clock duty cycle adjuster circuit for switched capacitor circuits," Electron. Lett., vol.38. no.18, pp.1008--9, Aug. 2002.
[2]
J. Doyle, Y.J. Lee, Y.-B. Kim, H. Wilsch, and F. Lombardi, "A CMOS subbandgap reference circuit with 1-V power supply voltage," IEEE J. Solid-State Circuits, vol.39, no.1, pp.252--255, Jan. 2004.
[3]
Lewis, S.H. and Gray, P.R., "A pipeline 5Msample/s 9bit analog-to-digital converter," IEEE JSSC, vol. SC-22, pp.954--61, Dec. 1987.
[4]
B. Song, S. Lee and M. F. Tompsett, "A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1328--1338, Dec. 1990.
[5]
C. R. Grace, P. J. Hurst and Stephen H. Lewis, "A 12-bit 80-MSample's Pipelined ADC with Bootstrapped Digital Calibration," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1038--46, May. 2005.
[6]
Sungjoon Kim, "A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL," IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 691--700, May. 1997.
[7]
J.G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723--1732, Nov. 1996.
[8]
J.N. Jang and H.J. Park, "An All--Digital CMOS Duty Cycle Correction Circuit with a duty cycle correction range of 15-to-85% for multi-phase applications," IEICE TRANS. Electron., Vol.E88-C, NO.4, pp.773-7, Apr. 2005.
[9]
B. Min, Y. Cho, H. Chae, H. Park and S. Lee, "A 10b 100MS/s 1.4mm2 56mW 0.18um CMOS A/D Converter with 3-D Fully Symmetrical Capacitors," IEICE Trans. on Electronics, vol. E89-C, no. 5, pp. 630--635, May 2006.

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    cover image ACM Conferences
    GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI
    May 2008
    480 pages
    ISBN:9781595939999
    DOI:10.1145/1366110
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 04 May 2008

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    Author Tags

    1. adc(analog-to-digital converter)
    2. cmos
    3. dll
    4. pipeline

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    May 4 - 6, 2008
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