It is our great pleasure to welcome you to the ACM SIGPLAN/SIGBED 2008 Conference on Languages, Compilers, and Tools for Embedded Systems -- LCTES 2008. This year's symposium continues its tradition of being the premier forum for presentation of research results on leading edge issues in embedded systems.
The call for papers attracted 68 submissions (40 from outside the United States) from all continents except Africa and Antarctica. Each submission was reviewed by at least three program committee members. The program committee meeting was held on March 1 2008 in Salt Lake City, Utah, USA. The program committee accepted 17 papers that cover a variety of topics, including programming languages, timing analysis, compiler optimization, and architectures.
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Flexible task graphs: a unified restricted thread programming model for java
The disadvantages of unconstrained shared-memory multi-threading in Java, especially with regard to latency and determinism in realtime systems, have given rise to a variety of language extensions that place restrictions on how threads allocate, share, ...
Enhanced hot spot detection heuristics for embedded java just-in-time compilers
Most Java just-in-time compilers (JITC) try to compile only hot methods since the compilation overhead is part of the running time. This requires precise and efficient hot spot detection, which includes distinguishing hot methods from cold methods, ...
Impact of JVM superoperators on energy consumption in resource-constrained embedded systems
Energy consumption is one of the most important issues in resource-constrained embedded systems. Many such systems run Java-based applications due to Java's architecture-independent format (bytecode). Standard techniques for executing bytecode programs, ...
Generalized instruction selection using SSA-graphs
Instruction selection is a well-studied compiler phase that translates the compiler's intermediate representation of programs to a sequence of target-dependent machine instructions optimizing for various compiler objectives (e.g. speed and space). Most ...
Compiler driven data layout optimization for regular/irregular array access patterns
Embedded multimedia applications consist of regular and irregular memory access patterns. Particularly, irregular pattern are not amenable to static analysis for extraction of access patterns, and thus prevent efficient use of a Scratch Pad Memory (SPM) ...
Relative competitive analysis of cache replacement policies
Caches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. On today's architectures a cache miss may cost several hundred CPU cycles.
In order to fulfill stringent performance requirements, ...
Robust and sustainable schedulability analysis of embedded software
For real-time systems, most of the analysis involves efficient or exact schedulability checking. While this is important, analysis is often based on the assumption that the task parameters such as execution requirements and inter-arrival times between ...
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors
While Ultra Deep Submicron (UDSM) CMOS scaling gives embedded processor designers ample silicon budget to increase processor resources to improve performance, restrictions with the power budget and practically achievable operating clock frequencies act ...
A domain specific interconnect for reconfigurable computing
Affine Control Loops (ACLs) occur frequently in data- and computeintensive applications. Implementing ACLs directly on dedicated hardware has the potential for spectacular performance improvement in area, time and energy. An important challenge for such ...
FaCSim: a fast and cycle-accurate architecture simulator for embedded systems
There have been strong demands for a fast and cycle-accurate virtual platforms in the embedded systems area where developers can do meaningful software development including performance debugging in the context of the entire platform. In this paper, we ...
A type system for the automatic distribution of higher-order synchronous dataflow programs
We address the design of distributed systems with synchronous dataflow programming languages. As modular design entails handling both architectural and functional modularity, our first contribution is to extend an existing synchronous dataflow ...
EventScript: an event-processing language based on regular expressions with actions
EventScript is a simple but powerful language for programming reactive processes. A stream of incoming events is matched against a regular expression. Actions embedded within the regular expression are executed in response to the matching of patterns of ...
Clock-directed modular code generation for synchronous data-flow languages
The compilation of synchronous block diagrams into sequential imperative code has been addressed in the early eighties and can now be considered as folklore. However, separate, or modular, code generation, though largely used in existing compilers and ...
Design and evaluation of a compiler for embedded stream programs
Applications that combine live data streams with embedded, parallel, and distributed processing are becoming more commonplace. WaveScript is a domain-specific language that brings high-level, type-safe, garbage-collected programming to these domains. ...
Post-pass periodic register allocation to minimise loop unrolling degree
This paper solves an open problem regarding loop unrolling after periodic register allocation. Although software pipelining is a powerful technique to extract fine-grain parallelism, it generates reuse circuits spanning multiple loop iterations. These ...
Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays
DSP architectures often feature multiple register files with sparse connections to a large set of ALUs. For such DSPs, traditional register allocation algorithms suffer from a lot of problems, including a lack of retargetability and phase-ordering ...
Optimizing scientific application loops on stream processors
This paper describes a graph coloring compiler framework to allocate on-chip SRF(Stream Register File) storage for optimizing scientific applications on stream processors. Our framework consists of first applying enabling optimizations such as loop ...
- Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems